公开(公告)号：US20130082328A1

公开(公告)日：2013-04-04

申请号：US13251783

申请日：2011-10-03

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78654

摘要： Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.

摘要翻译： 公开了包括应激源的晶体管器件。 一个这样的晶体管器件包括沟道区，电介质层和半导体衬底。 沟道区域被配置为在源极区域和漏极区域之间提供导电沟道。 此外，电介质层在沟道区下方，并被配置为使沟道区电绝缘。 此外，半导体衬底在沟道区域下方和介电层下方包括在半导体衬底的顶表面处的位错缺陷，其中位错缺陷共同定向以在沟道区域施加压缩应变，使得载流子 渠道区域的移动性得到增强。

公开(公告)号：US20130071979A1

公开(公告)日：2013-03-21

申请号：US13606382

申请日：2012-09-07

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

IPC分类号： H01L21/336

CPC分类号： H01L29/41783 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78654

摘要： A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.

摘要翻译： 一种用于制造场效应晶体管器件的方法，包括在衬底上形成栅极叠层，在衬底上邻近栅堆叠形成间隔物，在衬底上形成有源区的第一部分，有源区的第一部分 具有邻近所述栅叠层的第一刻面，在所述有源区的所述第一部分的一部分上形成所述有源区的第二部分，所述有源区的所述第二部分具有邻近所述栅叠层的第二刻面， 第一小面表面和第二小面表面部分地限定与栅极叠层相邻的空腔。

公开(公告)号：US08367544B2

公开(公告)日：2013-02-05

申请号：US12582137

申请日：2009-10-20

申请人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

IPC分类号： H01L21/44

CPC分类号： H01L21/76808 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76829

摘要： A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.

摘要翻译： 形成半导体器件的方法包括：图案化在待蚀刻的均匀半导体器件层上形成的光致抗蚀剂层; 对半导体器件进行注入工艺，该注入工艺根据待均匀半导体器件层内待蚀刻的特征的位置以及在要蚀刻的特征的期望深度选择性地埋入自对准的牺牲蚀刻停止层; 将由图案化的光致抗蚀剂层限定的特征图案蚀刻成均匀的半导体器件层，停止在注入的牺牲蚀刻停止层上; 以及在用填充材料填充蚀刻的特征图案之前去除注入的牺牲蚀刻停止层的剩余部分。

公开(公告)号：US08343877B2

公开(公告)日：2013-01-01

申请号：US12614952

申请日：2009-11-09

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L21/302

CPC分类号： H01L21/28132 ,  H01L21/26586 ,  H01L29/66787

摘要： A method for fabrication of features of an integrated circuit and device thereof include patterning a first structure on a surface of a semiconductor device and forming spacers about a periphery of the first structure. An angled ion implantation is applied to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions. The unprotected portions and the first structure are selectively removed with respect to the protected portions. A layer below the protected portions of the spacer is patterned to form integrated circuit features.

摘要翻译： 一种用于制造集成电路的特征的方法及其装置包括在半导体器件的表面上形成第一结构并在第一结构的周围形成间隔物。 将角度离子注入施加到器件，使得间隔物具有来自成角度离子注入的保护部分和未受保护部分，其中未保护部分具有大于被保护部分的蚀刻速率的蚀刻速率。 相对于受保护部分，非保护部分和第一结构被选择性地去除。 将间隔物的受保护部分下面的层图案化以形成集成电路特征。

公开(公告)号：US08338260B2

公开(公告)日：2012-12-25

申请号：US12760250

申请日：2010-04-14

申请人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam Shahidi

发明人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam Shahidi

IPC分类号： H01L21/336

CPC分类号： H01L29/78654 ,  H01L21/76283 ,  H01L29/66772 ,  H01L29/78618

摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.

摘要翻译： 提供一种晶体管，其包括衬底上方的掩埋氧化物层。 硅层在掩埋氧化物层之上。 栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。 氮化物衬垫与栅堆叠相邻。 氧化物衬垫与氮化物衬垫相邻。 一组具有包括硅层的一部分的部分的凸起的源/漏区。 所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

公开(公告)号：US20120322251A1

公开(公告)日：2012-12-20

申请号：US13597331

申请日：2012-08-29

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

IPC分类号： H01L21/28

CPC分类号： H01L29/42364 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

摘要： In one exemplary embodiment of the invention, a method (e.g., to fabricate a semiconductor device having a borderless contact) including: forming a first gate structure on a substrate; depositing an interlevel dielectric over the first gate structure; planarizing the interlevel dielectric to expose a top surface of the first gate structure; removing at least a portion of the first gate structure; forming a second gate structure in place of the first gate structure; forming a contact area for the borderless contact by removing a portion of the interlevel dielectric; and forming the borderless contact by filling the contact area with a metal-containing material.

摘要翻译： 在本发明的一个示例性实施例中，一种方法（例如，制造具有无边界接触的半导体器件）包括：在衬底上形成第一栅极结构; 在所述第一栅极结构上沉积层间电介质; 平面化所述层间电介质以暴露所述第一栅极结构的顶表面; 去除所述第一栅极结构的至少一部分; 形成第二栅极结构来代替第一栅极结构; 通过去除所述层间电介质的一部分来形成所述无边界接触的接触区域; 以及通过用含金属材料填充接触区域来形成无边界接触。

公开(公告)号：US08324036B2

公开(公告)日：2012-12-04

申请号：US12614986

申请日：2009-11-09

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

IPC分类号： H01L21/84

CPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

摘要： A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

摘要翻译： 一种用于制造用于集成电路的特征的方法包括图案化心轴层以包括在集成电路器件的表面上具有至少一个宽度的结构。 结构的暴露的侧壁反应以在侧壁中一体地形成新的化合物，使得新化合物以受控的量延伸到暴露的侧壁中以形成柱。 使用柱作为蚀刻掩模蚀刻柱下方的一个或多个层，以形成用于集成电路器件的特征。

公开(公告)号：US08318574B2

公开(公告)日：2012-11-27

申请号：US12847208

申请日：2010-07-30

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L21/20

CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/10867

摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having of a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion of the top silicon layer, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.

摘要翻译： 在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，背面带在背面的第一端耦合到顶部硅层的掺杂部分 带子和背部带子的第二端处的电容器; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。

公开(公告)号：US20120286364A1

公开(公告)日：2012-11-15

申请号：US13104542

申请日：2011-05-10

申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/8238

CPC分类号： H01L27/0727 ,  H01L21/823418 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203

摘要： A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.

摘要翻译： 一种方法包括在半导体衬底中形成隔离区以限定第一场效应晶体管（FET）区域，第二FET区域和二极管区域，在第一FET区域中形成第一栅极堆叠，在第二FET区域中形成第二栅极堆叠 FET区域，在所述第二FET区域和所述第二栅极堆叠上形成间隔材料层，在所述第一FET区域中形成第一源极区域和第一漏极区域，以及使用第一外延生长工艺在所述二极管区域中形成第一二极管层 在所述第一源极区域，所述第一漏极区域，所述第一栅极堆叠层和所述第一二极管层的一部分上形成硬掩模层，以及在所述第一FET区域中形成第二源极区域和第二漏极区域，以及在所述第一FET区域中形成第二二极管层 使用第二外延生长工艺在第一二极管层上。

公开(公告)号：US20120286350A1

公开(公告)日：2012-11-15

申请号：US13558518

申请日：2012-07-26

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

IPC分类号： H01L29/78

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78

摘要： An FET device characterized as being an asymmetrical tunnel FET (TFET) is disclosed. The TFET includes a gate-stack, a channel region underneath the gate-stack, a first and a second junction adjoining the gate-stack and being capable for electrical continuity with the channel. The first junction and the second junction are of different conductivity types. The TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side.

摘要翻译： 公开了一种以不对称隧道FET（TFET）为特征的FET器件。 TFET包括栅极堆叠，栅极堆叠下方的沟道区域，邻接栅极叠层的第一和第二结，并且能够与沟道电连接。 第一接头和第二接头具有不同的导电类型。 TFET还包括间隔物结构，使得栅极叠层的一侧上的间隔物形成比另一侧更薄。