公开(公告)号：US06812540B2

公开(公告)日：2004-11-02

申请号：US10298682

申请日：2002-11-19

申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L2900

CPC分类号： H01L27/105 ,  H01L27/10897

摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4−L5), (L6−L5), and (L4−L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有源区域nwp1和nw1之间的宽度为L4，有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

公开(公告)号：US06535435B2

公开(公告)日：2003-03-18

申请号：US10012522

申请日：2001-12-12

申请人： Hitoshi Tanaka ,  Masakazu Aoki ,  Shinichiro Kimura ,  Hiromasa Noda ,  Tomonori Sekiguchi

发明人： Hitoshi Tanaka ,  Masakazu Aoki ,  Shinichiro Kimura ,  Hiromasa Noda ,  Tomonori Sekiguchi

IPC分类号： G11C700

CPC分类号： H01L27/0222 ,  G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  H01L27/10897

摘要： A reference voltage generation circuit is provided which includes a p-channel type MOSFET used as an input transistor to allow a sufficient current to flow through a differential amplifier even if the threshold voltages of MOSFETs used in the differential amplifier significantly increase. A push-pull conversion circuit is coupled to the differential amplifier and has a double end configuration to provide a sufficiently high level to drive a p-channel output buffer. This arrangement allows a stable operation at a sufficiently low power supply voltage even if the threshold voltages of the MOSFETs forming the differential amplifier are high. It also allows quick activation when the power is turned on and provides high stability.

摘要翻译： 提供了一种参考电压产生电路，其包括用作输入晶体管的p沟道型MOSFET，以允许足够的电流流过差分放大器，即使差分放大器中使用的MOSFET的阈值电压显着增加。 推挽转换电路耦合到差分放大器并且具有双端配置以提供足够高的电平来驱动p沟道输出缓冲器。 即使形成差分放大器的MOSFET的阈值电压高，这种布置允许在足够低的电源电压下的稳定操作。 它还允许在电源打开时快速启动并提供高稳定性。

公开(公告)号：US06376304B1

公开(公告)日：2002-04-23

申请号：US09608154

申请日：2000-06-30

申请人： Hideyuki Matsuoka ,  Shinichiro Kimura ,  Toshiaki Yamanaka

发明人： Hideyuki Matsuoka ,  Shinichiro Kimura ,  Toshiaki Yamanaka

IPC分类号： H01L218242

CPC分类号： H01L27/10882 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

摘要： A semiconductor memory device and a method of fabricating the same are provided, in which an interlayer film which only covers a peripheral circuit region except a memory cell array is formed above the peripheral circuit region to reduce a topological difference between both regions after bitlines are formed; therefore, a semiconductor substrate which has a plain surface as a main one can be used as a starting body with no preliminary processing thereon and a shallow trench isolation technique can also be applied. Besides, interconnects to the peripheral circuit can be led up to the surface of the device through a multi-step plug connection and thereby processing of large aspect-ratio holes, the filling up of the holes with metal and the like are unnecessary and, as a result, reliability of the process is improved.

摘要翻译： 提供一种半导体存储器件及其制造方法，其中在外围电路区域之上形成仅覆盖存储单元阵列外的外围电路区域的层间膜，以减少在形成位线之后的两个区域之间的拓扑差异 ; 因此，以普通表面为主要的半导体衬底可以用作起始体，而不需要预处理，也可以应用浅沟槽隔离技术。 此外，与外围电路的互连可以通过多级插头连接引导到设备的表面，从而处理大的纵横比孔，用金属填充孔等是不必要的，因为 结果，改进了该过程的可靠性。

公开(公告)号：US6157055A

公开(公告)日：2000-12-05

申请号：US185633

申请日：1998-11-04

申请人： Ken Yamaguchi ,  Shinichiro Kimura ,  Masatada Horiuchi ,  Tatsuya Teshima

发明人： Ken Yamaguchi ,  Shinichiro Kimura ,  Masatada Horiuchi ,  Tatsuya Teshima

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/10808 ,  H01L27/10873

摘要： In a semiconductor memory device such as a DRAM, a conductive film (1.11') is arranged on the rim portion of a isolation insulating film (1.2) in opposition to a semiconductor substrate (1.1) with a thin insulating film in between. This conductive film (1.11') is electrically connected to a lower electrode (1.11) of a storage capacitor. This novel arrangement can control the location of electrical pn junction independently of the location of metallurgical pn junction, thereby realizing a semiconductor memory device having a long data retention time with the increase in leakage current suppressed.

摘要翻译： 在诸如DRAM的半导体存储器件中，在隔离绝缘膜（1.2）的与半导体衬底（1.1）相对的边缘部分上布置导电膜（1.11'），其间具有薄的绝缘膜。 该导电膜（1.11'）电连接到存储电容器的下电极（1.11）。 这种新颖的布置可以独立于冶金pn结的位置来控制电pn结的位置，从而实现了抑制泄漏电流增加的数据保持时间长的半导体存储器件。

公开(公告)号：US5270232A

公开(公告)日：1993-12-14

申请号：US943018

申请日：1992-09-10

申请人： Shinichiro Kimura ,  Shoji Shukuri ,  Hiromasa Noda ,  Digh Hisamoto ,  Hideyuki Matsuoka ,  Kazuyoshi Torii ,  Natsuki Yokoyama ,  Toshiyuki Yoshimura ,  Kazunori Tsujimoto ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Shoji Shukuri ,  Hiromasa Noda ,  Digh Hisamoto ,  Hideyuki Matsuoka ,  Kazuyoshi Torii ,  Natsuki Yokoyama ,  Toshiyuki Yoshimura ,  Kazunori Tsujimoto ,  Eiji Takeda

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/336 ,  H01L21/70

CPC分类号： H01L29/66606 ,  H01L21/28525 ,  H01L29/66621 ,  Y10S438/947

摘要： A very thin oxide film is formed at an opening formed in an insulator film and a conductor layer, on a substrate, and impurity-containing polysilicon is formed on the sidewall of the opening. Impurity diffusion from the from the silicon into the substrate through the very thin oxide film causes a lowering in effective concentration of the diffused impurities, resulting in the formation of shallower source/drain region. Thereafter, a gate insulator film and a gate electrode are formed on the substrate surface in an area bounded by an insulator film formed on the sidewall of the opening. The gate electrode smaller than the opening, the size of which corresponds to the limit of processing, and the shallower source/drain region afford a miniaturized MOSFET.

摘要翻译： 在基板上形成绝缘体膜和导体层的开口处形成非常薄的氧化膜，并且在开口的侧壁上形成含杂质的多晶硅。 通过非常薄的氧化膜从硅到衬底的杂质扩散导致扩散杂质的有效浓度降低，导致形成较浅的源/漏区。 此后，在由形成在开口的侧壁上的绝缘膜限定的区域中的基板表面上形成栅绝缘膜和栅电极。 小于开口的栅极电极，其尺寸对应于处理极限，并且较浅的源极/漏极区域提供小型化的MOSFET。

公开(公告)号：US5115289A

公开(公告)日：1992-05-19

申请号：US742196

申请日：1991-08-05

申请人： Dai Hisamoto ,  Toru Kaga ,  Shinichiro Kimura ,  Masahiro Moniwa ,  Haruhiko Tanaka ,  Atsushi Hiraiwa ,  Eiji Takeda

发明人： Dai Hisamoto ,  Toru Kaga ,  Shinichiro Kimura ,  Masahiro Moniwa ,  Haruhiko Tanaka ,  Atsushi Hiraiwa ,  Eiji Takeda

IPC分类号： H01L21/336 ,  H01L21/339 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/108 ,  H01L27/11 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L21/76264 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/1108 ,  H01L29/1062 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66954 ,  H01L29/78654 ,  H01L21/76278

摘要： A semiconductor device, such as an FET or a charge coupled device, is provided having a channel or a charge coupled portion formed in a thin semiconductor layer which is substantially perpendicular to the substrate. Necessary electrodes, such as the gate electrode, and necessary insulating layers can be added at the thin semiconductor layer, and can maintain the necessary amount of electric current by securing the height of the semiconductor layer. The structure has the advantage that it can have its plane size reduced. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.

摘要翻译： 提供了诸如FET或电荷耦合器件的半导体器件，其具有形成在基本上垂直于衬底的薄半导体层中的沟道或电荷耦合部分。 可以在薄的半导体层添加必要的电极，例如栅电极和必要的绝缘层，并且可以通过确保半导体层的高度来保持必要的电流量。 该结构具有能够减小其平面尺寸的优点。 此外，使用上述半导体器件的半导体存储器件适合于高集成度并且具有优异的电特性。

公开(公告)号：US4970564A

公开(公告)日：1990-11-13

申请号：US287881

申请日：1988-12-21

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10808

摘要： A semiconductor memory device having STC cells wherein major portions of active regions consisting of channel-forming portions are tilted at an angle of 45.degree. with respect to the word lines and the bit lines that meet at right angles with each other, enabling the storage capacity portions to be arranged very densely and sufficiently large capacities to be maintained with very small cell areas. In the semiconductor memory device, furthermore, the storage capacity portions are formed even on the bit lines. Therefore, the bit lines are shielded, the capacitance between the bit lines decreases, and the memory array noise decreases.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45°的角度倾斜，使得存储容量 部分布置得非常密集和足够大的容量保持非常小的单元格区域。 此外，在半导体存储器件中，即使在位线上形成存储容量部分。 因此，位线被屏蔽，位线之间的电容减小，并且存储器阵列噪声降低。

公开(公告)号：US4918502A

公开(公告)日：1990-04-17

申请号：US123235

申请日：1987-11-20

申请人： Toru Kaga ,  Shinichiro Kimura ,  Hideo Sunami

发明人： Toru Kaga ,  Shinichiro Kimura ,  Hideo Sunami

IPC分类号： H01L27/108

CPC分类号： H01L27/10829

摘要： The present invention relates to a highly packaged semiconductor memory, and more particularly to a memory cell having a trench capacitor for use in a CMOS memory. The present invention discloses a semiconductor memory employing memory cells each constructed of a trench type charge storage capacitor formed within a substrate, and a switching transistor; one electrode of the capacitor having a sheath-shaped structure which is electrically continuous with the Si substrate at a bottom of a groove and whose sideward periphery is covered with an insulator, the other electrode of the capacitor having a part which is buried inside the sheath electrode and another part which is electrically connected with an impurity diffused layer to function as a source region of the transistor. Further, a structure in which a voltage of 1/2 V.sub.cc can be applied to a plate electrode of a memory cell having a trench capacitor is disclosed.

摘要翻译： 本发明涉及高度封装的半导体存储器，更具体地说，涉及一种具有用于CMOS存储器的沟槽电容器的存储单元。 本发明公开了一种半导体存储器，其采用由形成在衬底内的沟槽型电荷存储电容器构成的存储单元和开关晶体管; 电容器的一个电极具有鞘状结构，其在沟槽的底部与Si衬底电连接，并且其侧面被绝缘体覆盖，电容器的另一个电极具有埋在护套内的部分 电极和与杂质扩散层电连接以用作晶体管的源极区的另一部分。 此外，公开了可以向具有沟槽电容器的存储单元的板电极施加1/2Vcc的电压的结构。

公开(公告)号：US4873560A

公开(公告)日：1989-10-10

申请号：US155698

申请日：1988-02-16

申请人： Hideo Sunami ,  Shinichiro Kimura ,  Toru Kaga

发明人： Hideo Sunami ,  Shinichiro Kimura ,  Toru Kaga

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10841 ,  Y10S257/922

摘要： This invention relates to a very large scale dynamic random access memory, and discloses a memory cell having a reduced step on the device surface portion and being hardly affected by incident radioactive rays. In a semiconductor memory consisting of a deep hole bored in a semiconductor substrate, a capacitor formed on the sidewall portion at the lower half of the deep hole and a switching transistor formed immediately above the capacitor, at least the half of a word line constituting the gate of the switching transistor is buried in an elongated recess formed at the surface portion of the semiconductor substrate.

摘要翻译： 本发明涉及一种非常大规模的动态随机存取存储器，并且公开了一种在器件表面部分上具有减小的步长并且几乎不受入射放射线影响的存储单元。 在由在半导体衬底中钻出的深孔组成的半导体存储器中，形成在深孔下半部分的侧壁部分上的电容器和形成在电容器上方的开关晶体管，至少形成一条字线的一半构成 开关晶体管的栅极被埋在形成在半导体衬底的表面部分处的细长凹部中。

公开(公告)号：US08472258B2

公开(公告)日：2013-06-25

申请号：US13269425

申请日：2011-10-07

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。