公开(公告)号：US20220415767A1

公开(公告)日：2022-12-29

申请号：US17929898

申请日：2022-09-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L23/495 ,  H01L23/40 ,  H01L23/00 ,  H01L25/065 ,  H01L23/367

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

公开(公告)号：US20220384204A1

公开(公告)日：2022-12-01

申请号：US17808338

申请日：2022-06-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Michael J. SEDDON ,  Yusheng LIN ,  Takashi NOMA ,  Eiji KUROSE

IPC: H01L21/3065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56

Abstract: Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

公开(公告)号：US20220351977A1

公开(公告)日：2022-11-03

申请号：US17813348

申请日：2022-07-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Yusheng LIN ,  Michael J. SEDDON ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L23/12

Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

公开(公告)号：US20220293499A1

公开(公告)日：2022-09-15

申请号：US17804423

申请日：2022-05-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jinchang ZHOU ,  Asif JAKWANI ,  Chee Hiong CHEW ,  Yusheng LIN ,  Sravan VANAPARTHY ,  Silnore Tejero SABANDO

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31

Abstract: Implementations of power modules may include: a substrate having a first side and a second side. The power module may include a plurality of leads coupled to a second side of the substrate and a molding compound over a portion of five or more surfaces of the substrate. The power module may also include an opening extending from a first side of the substrate to an outer edge of the molding compound. The opening may be configured to receive a coupling device and the coupling device may be configured to couple with a heat sink or a package support.

公开(公告)号：US20220270884A1

公开(公告)日：2022-08-25

申请号：US17662786

申请日：2022-05-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Michael J. SEDDON ,  Francis J. CARNEY ,  Takashi NOMA ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L21/48 ,  H01L23/31

Abstract: Implementations of a semiconductor package may include a semiconductor die including a first side and a second side, the first side of the semiconductor die including one or more electrical contacts; and an organic material covering at least the first side of the semiconductor die. Implementations may include where the one or more electrical contacts extend through one or more openings in the organic material; a metal-containing layer coupled to the one or more electrical contacts; and one or more slugs coupled to one of a first side of the semiconductor die, a second side of the semiconductor die, or both the first side of the semiconductor die and the second side of the semiconductor die.

公开(公告)号：US20220254734A1

公开(公告)日：2022-08-11

申请号：US17660941

申请日：2022-04-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Erik Nino TOLENTINO ,  Yusheng LIN ,  Swee Har KHOR

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/48

Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.

公开(公告)号：US20210320013A1

公开(公告)日：2021-10-14

申请号：US17304792

申请日：2021-06-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Yusheng LIN ,  Liangbiao CHEN

IPC: H01L21/48 ,  H01L23/28 ,  H01L21/56 ,  H01L23/495 ,  H01L23/498

Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

公开(公告)号：US20210272920A1

公开(公告)日：2021-09-02

申请号：US17320495

申请日：2021-05-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA ,  Kazuo OKADA ,  Hideaki YOSHIMI ,  Naoyuki YOMODA ,  Yusheng LIN

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/498

Abstract: Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.

公开(公告)号：US20210167112A1

公开(公告)日：2021-06-03

申请号：US16701533

申请日：2019-12-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA

IPC: H01L27/146

Abstract: Implementations of semiconductor packages may include: a substrate having a first side and a second side. The package may include a semiconductor package and a controller device coupled to the first side of the substrate through a tape or an adhesive. A molding compound may encapsulate the semiconductor device and the controller device. The package may also include a redistribution layer electrically coupling the semiconductor device and the controller device. An interconnect structure may be coupled with the redistribution layer. The package may include a solder resist layer coupled around the interconnect structure and over the molding compound, the semiconductor device, the controller device, and the copper redistribution layer.

公开(公告)号：US20210134606A1

公开(公告)日：2021-05-06

申请号：US16674279

申请日：2019-11-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Yusheng LIN ,  Liangbiao CHEN

IPC: H01L21/48 ,  H01L23/28 ,  H01L23/495 ,  H01L21/56

Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.