公开(公告)号：US10050062B2

公开(公告)日：2018-08-14

申请号：US15234155

申请日：2016-08-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Hidekazu Miyairi ,  Shunpei Yamazaki ,  Motomu Kurata

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/092 ,  H01L27/105 ,  H01L21/822 ,  H01L27/112

Abstract: A semiconductor device that occupies a small area and has a high degree of integration is provided. The semiconductor device includes a first insulating layer, a conductive layer, and a second insulating layer. The conductive layer is between the first insulating layer and the second insulating layer. The first insulating layer, the conductive layer, and the second insulating layer overlap with each other in a region. A contact plug penetrates the first insulating layer, the conductive layer, and the second insulating layer. In a depth direction from the second insulating layer to the first insulating layer, a diameter of the contact plug changes to a smaller value at an interface between the second insulating layer and the conductive layer.

公开(公告)号：US10002884B2

公开(公告)日：2018-06-19

申请号：US15584068

申请日：2017-05-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu Kurata ,  Ryota Hodo ,  Shinya Sasagawa ,  Yuki Hata

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/06 ,  H01L27/092 ,  H01L23/535

CPC classification number: H01L27/1207 ,  H01L21/8258 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To provide a semiconductor device which occupies a small area and is highly integrated. The semiconductor device includes an oxide semiconductor layer, an electrode layer, and a contact plug. The electrode layer includes one end portion in contact with the oxide semiconductor layer and the other end portion facing the one end portion. The other end portion includes a semicircle notch portion when seen from the above. The contact plug is in contact with the semicircle notch portion.

公开(公告)号：US09871059B2

公开(公告)日：2018-01-16

申请号：US14961061

申请日：2015-12-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo Isobe ,  Yutaka Okazaki ,  Kazuya Hanaoka ,  Shinya Sasagawa ,  Motomu Kurata

IPC: H01L29/10 ,  H01L29/24 ,  H01L27/12 ,  H01L27/11521 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L27/108 ,  H01L27/11

CPC classification number: H01L27/1225 ,  H01L27/10879 ,  H01L27/1104 ,  H01L27/11521 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.

公开(公告)号：US09698280B2

公开(公告)日：2017-07-04

申请号：US15062268

申请日：2016-03-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Motomu Kurata ,  Kazuya Hanaoka ,  Yoshiyuki Kobayashi ,  Daisuke Matsubayashi

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/04 ,  H01L29/24

Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.

公开(公告)号：US09553202B2

公开(公告)日：2017-01-24

申请号：US14489074

申请日：2014-09-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Motomu Kurata ,  Shinya Sasagawa ,  Ryota Hodo ,  Katsuaki Tochibayashi ,  Tomoaki Moriwaka ,  Jiro Nishida ,  Hidekazu Miyairi ,  Shunpei Yamazaki

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/5226 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/13 ,  H01L29/66969 ,  H01L29/7869

Abstract: The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.

Abstract translation: 半导体器件包括第一层，第一层包括第一晶体管，第二层，包括第一层上的第一绝缘膜，第三层，包括第二层上的第二绝缘膜;以及第四层，包括第三层上的第二晶体管 。 第一导电膜通过设置在第一绝缘膜中的开口将第一晶体管和第二晶体管彼此电连接。 第二导电膜通过设置在第二绝缘膜中的开口将第一晶体管，第二晶体管和第一导电膜彼此电连接。 第一晶体管的沟道形成区域包括单晶半导体。 第二晶体管的沟道形成区域包括氧化物半导体。 第二导电膜的底面的宽度为5nm以下。

公开(公告)号：US09437744B2

公开(公告)日：2016-09-06

申请号：US14197880

申请日：2014-03-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shinya Sasagawa ,  Motomu Kurata

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417 ,  H01L29/45 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78696

Abstract: When an oxide semiconductor film is microfabricated, with the use of a hard mask, unevenness of a side surface of the oxide semiconductor film can be suppressed. Specifically, a semiconductor device comprises an oxide semiconductor film over an insulating surface; a first hard mask and a second hard mask over the oxide semiconductor film; a source electrode over the oxide semiconductor film and the first hard mask; a drain electrode over the oxide semiconductor film and the second hard mask; a gate insulating film over the source electrode and the drain electrode; and a gate electrode overlapping with the gate insulating film and the oxide semiconductor film, and the first and second hard masks have conductivity.

Abstract translation: 当氧化物半导体膜被微细加工时，通过使用硬掩模，可以抑制氧化物半导体膜的侧表面的不均匀性。 具体地，半导体器件包括绝缘表面上的氧化物半导体膜; 氧化物半导体膜上的第一硬掩模和第二硬掩模; 所述氧化物半导体膜上的源电极和所述第一硬掩模; 所述氧化物半导体膜和所述第二硬掩模上的漏电极; 源电极和漏电极上的栅极绝缘膜; 以及与栅极绝缘膜和氧化物半导体膜重叠的栅电极，并且第一和第二硬掩模具有导电性。

公开(公告)号：US09299815B2

公开(公告)日：2016-03-29

申请号：US14626176

申请日：2015-02-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Motomu Kurata

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L21/441

CPC classification number: H01L29/66969 ,  H01L21/441 ,  H01L29/41733 ,  H01L29/7869

Abstract: An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.

公开(公告)号：US09287405B2

公开(公告)日：2016-03-15

申请号：US13632603

申请日：2012-10-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Motomu Kurata

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/78606 ,  H01L27/1156 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.

Abstract translation: 提供具有优异电特性的小型化晶体管，其产率高。 此外，以高生产率制造包括晶体管并且具有高性能和高可靠性的半导体器件。 在包括晶体管的半导体器件中，其中包括沟道形成区域的氧化物半导体膜和夹在沟道形成区域之间的低电阻区域，栅极绝缘膜和顶表面和侧表面被覆盖的栅极电极层 堆叠具有氧化铝膜的绝缘膜，源极电极层和漏电极层与氧化物半导体膜的一部分和顶面以及包含氧化铝膜的绝缘膜的侧面接触。

公开(公告)号：US09196744B2

公开(公告)日：2015-11-24

申请号：US14448024

申请日：2014-07-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Motomu Kurata ,  Hideaki Kuwabara ,  Mari Terashima

IPC: H01L29/12 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78696

Abstract: To provide a highly reliable semiconductor device including a transistor using an oxide semiconductor. After a source electrode layer and a drain electrode layer are formed, an island-like oxide semiconductor layer is formed in a gap between these electrode layers so that a side surface of the oxide semiconductor layer is covered with a wiring, whereby light is prevented from entering the oxide semiconductor layer through the side surface. Further, a gate electrode layer is formed over the oxide semiconductor layer with a gate insulating layer interposed therebetween and impurities are introduced with the gate electrode layer used as a mask. Then, a conductive layer is provided on a side surface of the gate electrode layer in the channel length direction, whereby an Lov region is formed while maintaining a scaled-down channel length and entry of light from above into the oxide semiconductor layer is prevented.

Abstract translation: 提供包括使用氧化物半导体的晶体管的高度可靠的半导体器件。 在形成源电极层和漏电极层之后，在这些电极层之间的间隙中形成岛状氧化物半导体层，使得氧化物半导体层的侧表面被布线覆盖，从而防止光 通过侧面进入氧化物半导体层。 此外，在氧化物半导体层上形成栅极电极层，其间插入有栅极绝缘层，并且将杂质与用作掩模的栅极电极层一起引入。 然后，在栅极电极层的沟道长度方向的侧面上设置导电层，由此形成Lov区，同时保持按比例缩小的沟道长度，并且防止从上方进入到氧化物半导体层的光。

公开(公告)号：US20140287552A1

公开(公告)日：2014-09-25

申请号：US14219111

申请日：2014-03-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Taiga Muraoka ,  Motomu Kurata ,  Shinya Sasagawa ,  Katsuaki Tochibayashi

IPC: H01L21/70 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/02554 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02565 ,  H01L21/02667 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/32139 ,  H01L29/66969 ,  H01L29/7869

Abstract: A stable and minute processing method of a thin film is provided. Further, a miniaturized semiconductor device is provided. A method for processing a thin film includes the following steps: forming a film to be processed over a formation surface; forming an organic coating film over the film to be processed; forming a resist film over the organic coating film; exposing the resist film to light_or_an electron beam; removing part of the resist film by development to expose part of the organic coating film; depositing an organic material layer on the top surface and a side surface of the resist film by plasma treatment; etching part of the organic coating film using the resist film and the organic material layer as masks to expose part of the film to be processed; and etching part of the film to be processed using the resist film and the organic material layer as masks.

Abstract translation: 提供了薄膜的稳定和微小的加工方法。 此外，提供了一种小型化的半导体器件。 一种处理薄膜的方法包括以下步骤：在地层表面上形成待处理的薄膜; 在待处理的膜上形成有机涂膜; 在有机涂膜上形成抗蚀膜; 将抗蚀剂膜暴露于light_or_an电子束; 通过显影去除部分抗蚀剂膜以暴露部分有机涂膜; 通过等离子体处理在抗蚀剂膜的顶表面和侧表面上沉积有机材料层; 使用所述抗蚀剂膜和所述有机材料层作为掩模蚀刻所述有机涂膜的一部分，以暴露待处理膜的部分; 并使用抗蚀剂膜和有机材料层作为掩模蚀刻待处理的膜的一部分。