公开(公告)号：US20180286951A1

公开(公告)日：2018-10-04

申请号：US15475946

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/324 ,  H01L21/225

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial mandrel structure above a semiconductor substrate comprising a first semiconductor material and forming a plurality of vertically-oriented channel semiconductor (VOCS) structures on at least opposing lateral sidewall surfaces of the sacrificial mandrel structure, the VOCS structures comprising a second semiconductor material that is different than the first semiconductor material. In this example, the method also includes selectively removing the sacrificial mandrel structure relative to the VOCS structures and forming upper and lower source/drain regions in each of the VOCS structures and a gate structure around each of the VOCS structures.

公开(公告)号：US10090385B1

公开(公告)日：2018-10-02

申请号：US15475946

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/324 ,  H01L21/225

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial mandrel structure above a semiconductor substrate comprising a first semiconductor material and forming a plurality of vertically-oriented channel semiconductor (VOCS) structures on at least opposing lateral sidewall surfaces of the sacrificial mandrel structure, the VOCS structures comprising a second semiconductor material that is different than the first semiconductor material. In this example, the method also includes selectively removing the sacrificial mandrel structure relative to the VOCS structures and forming upper and lower source/drain regions in each of the VOCS structures and a gate structure around each of the VOCS structures.

公开(公告)号：US20170263465A1

公开(公告)日：2017-09-14

申请号：US15598905

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L21/311 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/308 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/31144 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

Abstract: One illustrative device includes, among other things, at least one fin defined in a semiconductor substrate and a substantially vertical nanowire having an oval-shaped cross-section disposed on a top surface of the at least one fin.

公开(公告)号：US09698025B2

公开(公告)日：2017-07-04

申请号：US14476879

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L21/311 ,  H01L29/78 ,  H01L29/06 ,  H01L21/308 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8234

CPC classification number: H01L21/31144 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854

Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

公开(公告)号：US09455199B1

公开(公告)日：2016-09-27

申请号：US15044219

申请日：2016-02-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/8238 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a first fin for the PMOS device and a second fin for the NMOS device, wherein each of the first and second fins comprises a lower substrate fin portion and an upper fin portion that is made of semiconductor material that is different from that of the substrate, performing at least one process operation to form a first channel semiconductor material for the PMOS FinFET device that comprises a fully-strained, substantially defect-free substantially pure germanium material on a recessed upper surface of the upper fin portion of the first fin and form a second channel semiconductor material for the NMOS FinFET device that comprises a fully-relaxed substantially pure germanium material that is substantially defect free positioned above an upper surface of the lower substrate fin portion of the second fin.

Abstract translation: 本文公开的一种说明性方法包括形成用于PMOS器件的第一鳍片和用于NMOS器件的第二鳍片，其中第一鳍片和第二鳍片中的每一个包括下衬底鳍片部分和制成的上鳍片部分 的不同于衬底的半导体材料，执行至少一个处理操作以形成用于PMOS FinFET器件的第一沟道半导体材料，其包括在凹陷的上表面上的完全应变的，基本上无缺陷的基本上纯的锗材料 并且形成用于所述NMOS FinFET器件的第二沟道半导体材料，所述第二沟道半导体材料包括完全松弛的基本上纯的锗材料，其基本上无缺陷地位于所述第二鳍状物的下部衬底鳍部的上表面上方 鳍。

公开(公告)号：US20160254361A1

公开(公告)日：2016-09-01

申请号：US15154495

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

IPC: H01L29/49 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L29/45 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/51

CPC classification number: H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Abstract translation: 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。

公开(公告)号：US09425315B2

公开(公告)日：2016-08-23

申请号：US14811921

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/84 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L21/8238

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation region that vertically separates an upper portion of the initial fin structure from a semiconducting substrate, performing a recess etching process to remove a portion of the upper portion of the initial fin structure so as to define a recessed fin portion, forming a replacement fin on the recessed fin portion so as to define a final fin structure comprised of the replacement fin and the recessed fin portion, and forming a gate structure around at least a portion of the replacement fin.

Abstract translation: 本文公开的一种说明性方法包括氧化初始鳍结构的下部，从而限定将初始鳍结构的上部与半导体衬底垂直分离的隔离区，执行凹陷蚀刻工艺以去除 初始翅片结构的上部的一部分，以便限定一个凹入的翅片部分，在该凹入的翅片部分上形成一个替换翅片，以便限定由替换翅片和该凹入的翅片部分组成的最终翅片结构， 围绕替换翅片的至少一部分的门结构。

公开(公告)号：US20160204261A1

公开(公告)日：2016-07-14

申请号：US15073936

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Witold P. Maszara ,  Jody A. Fronheiser

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/30604 ,  H01L21/32133 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/51 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract translation: 公开了在半导体器件的沟道区域中形成外延半导体包层材料的一种方法，其包括围绕初始鳍片的一部分形成牺牲栅极结构，在牺牲栅极结构的相对侧上形成侧壁间隔物，并去除牺牲栅极 结构，从而限定替换栅极腔，通过替代栅极腔执行蚀刻工艺以去除初始翅片的部分，从而限定在侧壁间隔物下方的减小尺寸的翅片和凹陷，形成至少一个替代外延半导体 在更换的浇口腔体和侧壁间隙的凹槽内围绕减小尺寸的翅片的覆层材料，以及在至少一个替代的外延半导体包层材料周围的置换栅极腔内形成替换栅极结构。

公开(公告)号：US09343300B1

公开(公告)日：2016-05-17

申请号：US14686857

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Michael Hargrove ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/66 ,  H01L21/324 ,  H01L29/167 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/225

CPC classification number: H01L29/66636 ,  H01L21/02579 ,  H01L21/02694 ,  H01L21/2251 ,  H01L21/2257 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/165 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: The present disclosure is directed to forming relatively abrupt junctions between the channel region and source/drain regions of a PMOS transistor device with a germanium-containing channel region. A liner layer is formed in previously formed source/drain cavities prior to the formation of epi semiconductor material in the source/drain cavities above the liner layer. The materials for the liner layer and, particularly, the concentration of germanium (if any is present) are adjusted relative to the germanium concentration in the channel region and the epi source/drain material such that, during an anneal process, dopant materials (e.g., boron) that diffuse from the source/drain region during the anneal process tend to accumulate in or near the liner layer.

Abstract translation: 本公开涉及在具有含锗沟道区的PMOS晶体管器件的沟道区域和源极/漏极区域之间形成相对突然的结。 在预先形成的源/漏腔之前，在衬层之上的源极/漏极腔中形成外延半导体材料之前形成衬层。 用于衬里层的材料，特别是锗的浓度（如果有的话）相对于沟道区域和外延源/漏极材料中的锗浓度进行调节，使得在退火过程期间，掺杂剂材料（例如 ，硼）在退火工艺期间从源极/漏极区扩散倾向于积聚在衬里层中或其附近。

公开(公告)号：US20160118251A1

公开(公告)日：2016-04-28

申请号：US14525351

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of P-type dopant material and the other of the first and second layers has a low level of germanium and a high level of P-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of P-type dopant material.

Abstract translation: 本文中公开的一种说明性方法包括进行第一和第二原位掺杂，外延沉积工艺以分别在半导体衬底之上形成第一和第二层原位掺杂的外延半导体材料，其中第一和第二 层具有高水平的锗和低水平的P型掺杂剂材料，并且第一和第二层中的另一层具有低水平的锗和高水平的P型掺杂剂材料，并且进行混合热退火工艺 在第一和第二层上形成具有高水平的锗和高水平的P型掺杂剂材料的最终硅锗材料。