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295 条记录 (耗时 0.027 秒)

    Magnetic disk system and waveform equalizer therefor
    83.
    发明授权
    Magnetic disk system and waveform equalizer therefor 失效
    磁盘系统及其波形均衡器

    公开(公告)号：US5463504A

    公开(公告)日：1995-10-31

    申请号：US62770

    申请日：1993-05-18

    申请人： Hiroshi Kimura ,  Shoichi Miyazawa ,  Ryutaro Horita ,  Kenichi Hase ,  Akihiko Hirano ,  Akira Uragami

    发明人： Hiroshi Kimura ,  Shoichi Miyazawa ,  Ryutaro Horita ,  Kenichi Hase ,  Akihiko Hirano ,  Akira Uragami

    IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14

    CPC分类号： G11B20/10046 ,  G11B20/10009 ,  G11B20/10222 ,  G11B20/1403 ,  G11B5/012 ,  G11B5/09 ,  G11B20/1258

    摘要： A magnetic disk system which records and reproduces data on a magnetic disk at different data transfer rates depending on a track position on the disk includes a transversal waveform equalizing circuit which implements an optimal waveform shaping for a readout waveform. The waveform equalizing circuit consists of a register, a frequency synthesizer, a PLL, and a transversal circuit. The transversal circuit consists of variable delay circuits, variable gain amplifiers, and an adder. The frequency synthesizer produces a write clock signal having a frequency which corresponds to a value stored in the register which depends on the data transfer rate, and the PLL responds to the write clock signal to produce a control signal by which the delay time of the transversal circuit is controlled. Consequently, the delay characteristic is not affected by disparity of circuit components of the transversal circuit, and the write clock frequency and the delay time of the transversal circuit can be set to intended values by merely changing the value stored in the register in response to a variation of the data transfer rate.

    摘要翻译： 根据磁盘上的轨道位置以不同的数据传输速率记录和再现磁盘上的数据的磁盘系统包括对读出波形实现最佳波形整形的横向波形均衡电路。 波形均衡电路由寄存器，频率合成器，PLL和横向电路组成。 横向电路由可变延迟电路，可变增益放大器和加法器组成。 频率合成器产生具有对应于存储在寄存器中的取决于数据传输速率的值的频率的写时钟信号，并且PLL响应于写时钟信号以产生控制信号，通过该控制信号，横向延迟时间 电路被控制。 因此，延迟特性不受横向电路的电路部件的不均匀影响，并且横向电路的写入时钟频率和延迟时间可以通过仅响应于一个变化来改变存储在寄存器中的值来设置为预期值 数据传输速率的变化。

    Method of making semiconductor device including MOS type field effect transistor
    84.
    发明授权
    Method of making semiconductor device including MOS type field effect transistor 失效
    制造包括MOS型场效应晶体管的半导体器件的方法

    公开(公告)号：US5436178A

    公开(公告)日：1995-07-25

    申请号：US186495

    申请日：1994-01-26

    申请人： Hiroshi Kimura

    发明人： Hiroshi Kimura

    IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/36 ,  H01L21/265

    CPC分类号： H01L29/66575 ,  H01L29/0847 ,  H01L29/36

    摘要： A semiconductor device includes an MOS field effect transistor having a structure in which the tops of its source/drain regions are covered with a polycrystalline silicon layer. The impurity concentration distribution in its depth direction of the source/drain regions of the MOS field effect transistor is such that the concentration is sufficiently high in an area necessary to have conductivity a prescribed depth away from the surface of the semiconductor substrate, and the impurity concentration drastically decreases in areas deeper than that. Thus, a punch through phenomenon in positions relatively deep in the channel region is suppressed, and an MOS field effect transistor having its channel length reduced to 0.5 .mu.m and less and achieving high performance can be obtained. Such an MOS field effect transistor can be produced by implanting an impurity a number of times, controlling appropriately the peak value and the peak position of the impurity concentration, before and after or only after the formation of the polycrystalline silicon layer.

    摘要翻译： 半导体器件包括具有其源极/漏极区域的顶部被多晶硅层覆盖的结构的MOS场效应晶体管。 MOS场效应晶体管的源极/漏极区域的深度方向的杂质浓度分布使得在距离半导体衬底的表面具有规定深度的导电性所需的区域中的浓度足够高，并且杂质 浓度急剧下降。 因此，抑制了沟道区域相对较深的位置的穿孔现象，可以获得沟道长度减小到0.5μm以下并实现高性能的MOS场效应晶体管。 这样的MOS场效应晶体管可以通过在多晶硅层的形成之前和之后或之后适当地注入杂质多次来适当地控制杂质浓度的峰值和峰值位置来产生。

    Semiconductor device and a manufacturing method thereof
    86.
    发明授权
    Semiconductor device and a manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US5378650A

    公开(公告)日：1995-01-03

    申请号：US6394

    申请日：1993-01-21

    申请人： Hiroshi Kimura

    发明人： Hiroshi Kimura

    IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L21/76

    CPC分类号： H01L29/66765 ,  H01L29/42384 ,  H01L29/78624 ,  H01L29/78636

    摘要： A semiconductor device includes a semiconductor substrate having a main surface, an isolating insulator film formed on the main surface and having a substantially vertical side wall, a plurality of semiconductor element regions, which are separated from each other by the isolating insulator film, for forming semiconductor circuit elements therein, a first impurity region formed in the substrate to a predetermined depth from an interface between the isolating insulator film and the substrate by ion implantation, second impurity regions formed in the element regions simultaneously with the first impurity region by the ion implantation and located at a predetermined depth from the main surface, and a side wall insulator film formed by anisotropic etching on the vertical wall of the isolating insulator film.

    摘要翻译： 半导体器件包括具有主表面的半导体衬底，形成在主表面上并具有基本上垂直的侧壁的隔离绝缘膜，通过隔离绝缘膜彼此分离的多个半导体元件区域，用于形成 在其中的半导体电路元件，通过离子注入在衬底中形成到隔离绝缘膜和衬底之间的界面到预定深度的第一杂质区，通过离子注入在元件区中与第一杂质区同时形成的第二杂质区 并且位于距离主表面的预定深度处，以及通过各向异性蚀刻在隔离绝缘膜的垂直壁上形成的侧壁绝缘膜。

    Folding circuit and analog-to-digital converter
    88.
    发明授权
    Folding circuit and analog-to-digital converter 失效
    折叠电路和模数转换器

    公开(公告)号：US5307067A

    公开(公告)日：1994-04-26

    申请号：US47480

    申请日：1993-04-19

    申请人： Hiroshi Kimura ,  Akira Matsuzawa

    发明人： Hiroshi Kimura ,  Akira Matsuzawa

    IPC分类号： H03M1/36

    CPC分类号： H03M1/36

    摘要： By making a folded waveform of a folding circuit sharp, the number of elements used in an ADC is reduced and less power consumption is achieved. A folding circuit is composed of a plurality of master-comparator latches, a pair of wiring means for master-to-slave connection, and a slave latch. By means of the wiring means, the non-inverted outputs and the inverted outputs of the master-comparators latches are alternately drawn in the order of magnitude of reference voltages, superimposed, and fed into a pair of inputs of the slave latch. A Gray code signal is directly encoded by an encoder according to the output of the slave latch. A folded signal, which is the output of the folding circuit, takes a sharp waveform. The number of slave latches can be reduced. No XOR gates are required.

    摘要翻译： 通过使折叠电路的折叠波形清晰，ADC中使用的元件数量减少，功耗降低。 折叠电路由多个主比较器锁存器，一对用于主从连接的布线装置和从锁存器组成。 通过布线装置，主比较器锁存器的非反相输出和反相输出交替地以参考电压的数量级叠加并被馈送到从锁存器的一对输入。 格雷码信号由编码器根据从锁存器的输出直接编码。 作为折叠电路的输出的折叠信号采用尖锐的波形。 可以减少从锁存器的数量。 不需要XOR门。

    Chemical sensor for carbon monoxide detection
    89.
    发明授权
    Chemical sensor for carbon monoxide detection 失效
    一氧化碳检测用化学传感器

    公开(公告)号：US5252949A

    公开(公告)日：1993-10-12

    申请号：US751029

    申请日：1991-08-28

    申请人： Kevin W. Kirby ,  Hiroshi Kimura ,  Ricardo C. Pastor

    发明人： Kevin W. Kirby ,  Hiroshi Kimura ,  Ricardo C. Pastor

    IPC分类号： G01N27/12 ,  G01N33/00 ,  G08B17/10

    CPC分类号： G01N27/12 ,  G01N33/004

    摘要： A ceramic sensor (12) comprising a thin film (14) of Cu.sub.1=x Mn.sub.2-x O.sub.4-y is provided that quantitatively measures the partial pressure of CO gas in a flowing system (22). The sensor is specific to CO gas and is negligibly affected by the presence of the common automobile exhaust vapors NO, H.sub.2 O, and CH.sub.4, within the operational temperature range from about 250.degree. to 450.degree. C. The CO sensor of the invention has other applications, such as monitoring CO levels in laboratories, mines, and industrial smoke stacks, and may be used in environments up to about 700.degree. C.

    Method of manufacturing stacked capacitor type semiconductor memory device
    90.
    发明授权
    Method of manufacturing stacked capacitor type semiconductor memory device 失效
    叠层电容器型半导体存储器件的制造方法

    公开(公告)号：US5180683A

    公开(公告)日：1993-01-19

    申请号：US727781

    申请日：1991-07-10

    申请人： Wataru Wakamiya ,  Yoshinori Tanaka ,  Takahisa Eimori ,  Hiroji Ozaki ,  Hiroshi Kimura ,  Shinichi Satoh

    发明人： Wataru Wakamiya ,  Yoshinori Tanaka ,  Takahisa Eimori ,  Hiroji Ozaki ,  Hiroshi Kimura ,  Shinichi Satoh

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10817

    摘要： A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor had various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

    摘要翻译： 根据本发明的半导体存储器件包括具有一个晶体管和一个堆叠电容器的存储单元。 堆叠的电容器堆叠在半导体衬底的表面上。 此外，层叠电容器具有通过绝缘层在栅电极和字线上延伸的结构。 电容器的下电极层具有各种凹凸形状，即台阶部分和形成在其表面上的突出部分。 这些形状通过采用各种蚀刻工艺制成。 下电极层在其上形成有各种凹凸形状，从而能够提高电容器的表面积和电容。