公开(公告)号：US5319586A

公开(公告)日：1994-06-07

申请号：US18343

申请日：1993-02-16

申请人： Subhash Gupta ,  Ravi Mehrotra

发明人： Subhash Gupta ,  Ravi Mehrotra

IPC分类号： G06F17/12 ,  G06F17/16 ,  G06F15/32 ,  G06F7/00

CPC分类号： G06F17/12 ,  G06F17/16

摘要： An apparatus and method for performing matrix calculations is provided. The apparatus comprises a computer system having a linearly connected array of processors. Each processor has three inputs, two of which receive data along the linear array. The processors are configured to perform certain multiply-add operations. The methods permit speeded up solution of systems of linear equations and matrix inversion. The methods involve manipulating the matrices and the unknown vector values such that the problem can be solved using vector orthogonalization techniques.

摘要翻译： 提供了一种用于执行矩阵计算的装置和方法。 该装置包括具有线性连接的处理器阵列的计算机系统。 每个处理器有三个输入，其中两个输入沿线性阵列接收数据。 处理器被配置为执行某些乘法加法操作。 该方法允许加速线性方程组和矩阵反演系统的解。 该方法涉及操纵矩阵和未知向量值，使得可以使用向量正交化技术来解决问题。

公开(公告)号：US5198298A

公开(公告)日：1993-03-30

申请号：US426147

申请日：1989-10-24

申请人： Jacob D. Haskell ,  Subhash Gupta

发明人： Jacob D. Haskell ,  Subhash Gupta

IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/76801 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76834 ,  Y10S438/97 ,  Y10T428/265 ,  Y10T428/31612 ,  Y10T428/31663

摘要： An etch stop player (22) for permitting distinguishing between two similar layers (20, 24), such as two oxide layers, during etching is provided. The etch stop layer comprises a silicon-oxyhalide polymer, preferably a silicon-oxyfluoride polymer. Use of the polymer as an etch stop layer permits closer placement of metal conductor surfaces (12, 12') and contacts (14').

摘要翻译： 提供了用于允许在蚀刻期间区分两个相似层（20,24）（例如两个氧化物层）的蚀刻停止播放器（22）。 蚀刻停止层包括硅 - 卤氧化物聚合物，优选硅 - 氟氧化物聚合物。 使用聚合物作为蚀刻停止层允许金属导体表面（12,12'）和触点（14'）的更靠近的放置。

公开(公告)号：US4992134A

公开(公告)日：1991-02-12

申请号：US436282

申请日：1989-11-14

申请人： Subhash Gupta ,  Kashmir Sahota

发明人： Subhash Gupta ,  Kashmir Sahota

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/3065 ,  H01L21/32137

摘要： A plasma etching process is provided which etches n-type, p-type, and intrinsic polysilicon on the same wafer at substantially the same rate. Native oxide is first removed by etching in a conventional oxide etchant, such as SiCl.sub.4 /Cl.sub.2, BCl.sub.3 /Cl.sub.2, CCl.sub.4, other mixtures of fluorinated or chlorinated gases, and mixtures of Freon-based gases. The polysilicon is then etched in an etchant comprising at least about 75% hydrogen and the balance a halogen-containing fluid, such as chloride. The silicon etchant etches at a rate of about 300 to 500 .ANG. for a batch of 10 wafers, depending on hydrogen concentration, power, flow rate of gas mixture, and gas pressure.

公开(公告)号：US06380084B1

公开(公告)日：2002-04-30

申请号：US09678621

申请日：2000-10-02

申请人： Yeow Kheng Lim ,  Alex See ,  Cher Liang Cha ,  Subhash Gupta ,  Wang Ling Goh ,  Man Siu Tse

发明人： Yeow Kheng Lim ,  Alex See ,  Cher Liang Cha ,  Subhash Gupta ,  Wang Ling Goh ,  Man Siu Tse

IPC分类号： H01L2144

CPC分类号： H01L21/76844 ,  H01L21/32051 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form robust dual damascene interconnects by decoupling via and connective line trench filling has been achieved. A first dielectric layer is deposited overlying a silicon nitride layer. A shielding layer is deposited. The shielding layer, the first dielectric layer, and the silicon nitride layer are patterned to form via trenches. A first barrier layer is deposited to line the trenches. The via trenches are filled with a first copper layer by a single deposition or by depositing a seed layer and then electroless or electrochemical plating. The first copper layer is polished down to complete the vias. A second barrier layer is deposited. The second barrier layer is patterned to form via caps. A second dielectric layer is deposited. A capping layer is deposited. The capping layer and the second dielectric layer are patterned to form connective line trenches that expose a part of the via caps. A third barrier layer is deposited to line the connective line trenches. The third barrier layer and the via caps are etched to form trench barrier sidewall spacers and to expose the vias. The connective line trenches are filled with a second copper layer by a single deposition, by a first deposition of a seed layer followed by plating, or by plating using the via as the seed layer. The second copper layer is polished down.

摘要翻译： 已经实现了通过解耦通孔和连接线沟槽填充形成鲁棒的双镶嵌互连的方法。 沉积在氮化硅层上的第一介电层。 屏蔽层被沉积。 将屏蔽层，第一介电层和氮化硅层图案化以形成通孔沟槽。 沉积第一势垒层以对沟槽进行排列。 通过单个沉积或通过沉积种子层然后进行无电镀或电化学电镀，将通孔沟槽填充有第一铜层。 第一个铜层被抛光以完成通孔。 沉积第二阻挡层。 图案化第二阻挡层以形成通孔。 沉积第二介电层。 沉积覆盖层。 图案化覆盖层和第二介电层以形成连接线沟槽，其暴露通孔盖的一部分。 沉积第三阻挡层以对连接线沟槽进行排列。 蚀刻第三阻挡层和通孔盖以形成沟槽阻挡侧壁间隔件并露出通孔。 连接线沟槽通过单次沉积，通过第一次沉积种子层，然后电镀，或通过使用通孔作为种子层进行电镀，填充第二铜层。 第二个铜层被抛光。

公开(公告)号：US6040619A

公开(公告)日：2000-03-21

申请号：US937774

申请日：1997-09-25

申请人： Fei Wang ,  David K. Foote ,  Myron R. Cagan ,  Subhash Gupta

发明人： Fei Wang ,  David K. Foote ,  Myron R. Cagan ,  Subhash Gupta

IPC分类号： H01L21/28 ,  H01L21/027 ,  H01L21/312 ,  H01L21/314 ,  H01L21/318 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/11 ,  H01L29/78 ,  H01L23/58 ,  H01L21/316 ,  H01L23/48

CPC分类号： H01L21/0276 ,  H01L21/3121 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002

摘要： A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.

摘要翻译： 在半导体衬底上形成诸如金属氧化物半导体（MOS）晶体管的微电子器件。 用于器件的钨镶嵌互连使用具有大约40％至50％重量比的高硅含量的氮化硅，氮氧化硅或硅肟的蚀刻停止层形成。 蚀刻停止层相对于上覆绝缘体材料如二氧化硅，原硅酸四乙酯（TEOS）玻璃和硼磷硅酸盐玻璃（BPSG）具有高蚀刻选择性。 蚀刻停止层还具有高折射率并且是抗反射性的，从而改善光刻成像期间的临界尺寸控制。

公开(公告)号：US5658440A

公开(公告)日：1997-08-19

申请号：US553966

申请日：1995-11-06

申请人： Michael K. Templeton ,  Subhash Gupta

发明人： Michael K. Templeton ,  Subhash Gupta

IPC分类号： G03F7/40 ,  H01J37/32 ,  H01L21/3213 ,  C23C14/34

CPC分类号： H01J37/32192 ,  G03F7/40 ,  H01J37/32678 ,  H01L21/32137

摘要： A process called surface image transfer etching (SITE) is used to etch patterned photoresist so as to more completely transfer a well-defined pattern formed in the top surface (10a) of a material to the bulk of the material (12). The process uses no mask, but employs only a sputter etching process where the etching rates of surfaces not normal to the ion trajectories are greatly enhanced over the etching rates of surfaces normal to the ion trajectories.

摘要翻译： 使用称为表面图像转移蚀刻（SITE）的工艺来蚀刻图案化的光致抗蚀剂，以便将形成在材料的顶表面（10a）中的良好限定的图案更完全地转移到材料（12）的主体上。 该方法不使用掩模，而仅使用溅射蚀刻工艺，其中不垂直于离子轨迹的表面的蚀刻速率比垂直于离子轨迹的表面的蚀刻速率大大增强。

公开(公告)号：US5614765A

公开(公告)日：1997-03-25

申请号：US478319

申请日：1995-06-07

申请人： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

发明人： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1036 ,  H01L2924/0002

摘要： An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as self aligned mask for etching via openings. The conformal material is either a conductive material which is left in place after the via openings are formed or an insulating material which is removed. In the former, the partially filled conductive line openings are filled with additional conductive material along with the via, which is either the same or different conductive material. In the latter, the conductive line openings and vias are filled with the same conductive material.

摘要翻译： 用于集成电路和用于半导体器件的衬底载体的绝缘分隔的导线和连接通孔的互连级别，使用双镶嵌仅具有一个掩模图案以形成导电线和通孔。 导电线的掩模图案包含​​在绝缘材料中要形成通孔开口的横向扩大区域。 在产生具有横向扩大区域的导电线路开口之后，开口用适形材料填充，其保护材料的蚀刻选择性基本上小于绝缘材料对用于蚀刻绝缘材料的附魔的蚀刻选择性，并且其蚀刻选择性基本上大于 绝缘材料到其附魔。 保形材料被各向异性地蚀刻以在扩大区域中形成侧壁并且移除侧壁之间的材料，而留下留在导电线开口部分中的材料。 侧壁用作通过开口蚀刻的自对准掩模。 保形材料是导电材料，其在形成通孔开口之后留在适当位置或者被去除的绝缘材料。 在前者中，部分填充的导电线路开口与另外的导电材料一起填充，该通孔是相同或不同的导电材料。 在后者中，导电线路开口和通孔用相同的导电材料填充。

公开(公告)号：US5468340A

公开(公告)日：1995-11-21

申请号：US159634

申请日：1993-11-30

申请人： Subhash Gupta ,  Susan Chen ,  Angela Hui

发明人： Subhash Gupta ,  Susan Chen ,  Angela Hui

IPC分类号： C23F4/00 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L21/00 ,  H05H1/00

CPC分类号： H01L21/76805 ,  H01L21/31116 ,  H01L21/76816

摘要： A method for rapid anisotropic dry etching of oxide compounds in high aspect ratio openings which etching method is highly selective to metal salicides and which method employs plasma gases of CHF.sub.3, N.sub.2 and a high flow rate of He at a high pressure and products made by the process.

摘要翻译： 一种用于在高纵横比开口中快速各向异性干蚀刻氧化物化合物的方法，其蚀刻方法对金属杀锌剂具有高选择性，并且哪种方法使用CHF 3，N 2等离子体气体和高流量的He，以及由 处理。

公开(公告)号：US5308740A

公开(公告)日：1994-05-03

申请号：US947242

申请日：1992-09-18

申请人： Michael K. Templeton ,  Subhash Gupta

发明人： Michael K. Templeton ,  Subhash Gupta

IPC分类号： G03F7/26 ,  G03C5/00 ,  B44C1/22

CPC分类号： G03F7/26

摘要： A method for measuring the sidewall angle of patterned photoresist (16), as well as wall angles of other materials, is provided. The method comprises forming two copies of the patterned photoresist feature for which the sidewall measurement is to be obtained on a conducting substrate (14). The first copy is processed via conventional techniques for linewidth measurement, which consists of a pattern transfer etch of the first copy into the underlying conductive substrate, followed by electrical measurement of the conductor linewidth to yield linewidth 1 (LW1). The second copy is processed such that there is a shape altering etch prior to the pattern transfer etch. A linewidth 2 (LW2) is obtained. The angle is then extracted from the two linewidth measurements.

摘要翻译： 提供了用于测量图案化光致抗蚀剂（16）的侧壁角以及其它材料的壁角的方法。 该方法包括在导电衬底（14）上形成要获得侧壁测量的图案化光致抗蚀剂特征的两个拷贝。 通过用于线宽测量的常规技术来处理第一个拷贝，该技术包括将第一拷贝的图案转移蚀刻到下面的导电衬底中，随后电导体线宽的线性测量以产生线宽1（LW1）。 处理第二拷贝使得在图案转移蚀刻之前存在改变蚀刻的形状。 得到线宽2（LW2）。 然后从两个线宽测量中提取角度。

公开(公告)号：US5260868A

公开(公告)日：1993-11-09

申请号：US776713

申请日：1991-10-15

申请人： Subhash Gupta ,  Sanjiv S. Sidhu ,  Frank Vlach

发明人： Subhash Gupta ,  Sanjiv S. Sidhu ,  Frank Vlach

IPC分类号： G05B19/418 ,  G06Q10/06 ,  G07C3/00 ,  G06F15/20

CPC分类号： G06Q10/06 ,  G05B19/41865 ,  G07C3/00 ,  G05B2219/34418 ,  Y02P90/20

摘要： A mechanism and method for calendaring a plurality of events such as scheduling the operation of interrelated machines which perform a process flow. Future time is divided into segments, called buckets, of increasing length. The first two buckets are of the same size and each of the following buckets twice as large as its preceding bucket. The first bucket slides so as to always cover a specified length of time following the current time. Events scheduled in the calendar is added to the appropriate bucket, depending on how far in the future it is to take place. When the current time equals the scheduled time for an event, then that event is removed from the bucket where it resides. When a bucket has become empty because all events have been removed from it, the events in the following bucket are distributed over the two buckets preceding it.

摘要翻译： 一种用于对多个事件进行日历的机制和方法，例如调度执行处理流程的相互关联的机器的操作。 未来时间被分为长度增长的段，称为桶。 前两个桶的尺寸相同，以下桶中的每一个都是前一桶的两倍。 第一个铲斗滑动，以便在当前时间之后始终覆盖指定的时间长度。 日程安排的活动将添加到相应的存储桶中，具体取决于将来发生的时间。 当当前时间等于事件的预定时间时，该事件将从它驻留的存储桶中删除。 当桶已经变为空时，因为所有事件都已从其中删除，下一个桶中的事件将分布在其前面的两个桶中。