公开(公告)号：US20240387491A1

公开(公告)日：2024-11-21

申请号：US18455857

申请日：2023-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen

IPC: H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A method includes bonding a module over a package component. The module includes a substrate and through-vias penetrating through the substrate. The method further includes molding the module in a molding compound, bonding an electronic die on the module, and bonding a photonic die over the electronic die.

公开(公告)号：US20240387452A1

公开(公告)日：2024-11-21

申请号：US18785335

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/768 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

公开(公告)号：US20240385395A1

公开(公告)日：2024-11-21

申请号：US18467020

申请日：2023-09-14

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Ming-Fa Chen ,  Shang-Yun Hou

IPC: G02B6/42

Abstract: In an embodiment, a method includes: forming an optical package, forming the optical package comprising: forming optical devices over a substrate; forming a first interconnect structure over the optical devices; and attaching a first semiconductor device to the optical devices; attaching a second semiconductor device to an interposer substrate; attaching the optical package to the interposer substrate; and attaching an optical port adjacent to the optical package, the optical port comprising: an optical fiber; and an optical redirection structure configured to redirect an optical signal between a first pathway and a second pathway, the first pathway being parallel with a major surface of the interposer substrate, the second pathway being non-parallel with the major surface of the interposer substrate.

公开(公告)号：US20240379614A1

公开(公告)日：2024-11-14

申请号：US18782253

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Cheng-Feng Chen ,  Sung-Feng Yeh ,  Chuan-An Cheng

IPC: H01L23/00 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065

Abstract: In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.

公开(公告)号：US20240377587A1

公开(公告)日：2024-11-14

申请号：US18783031

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen

IPC: G02B6/13 ,  G02B6/12 ,  G02B6/124 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528

Abstract: A packaged device includes an optical IC having an optical feature therein. An interconnect structure including layers of conductive features embedded within respective layers of dielectric materials overlie the optical feature. The interconnect structure is patterned to remove the interconnect structure from over the optical feature and a dielectric material having optically neutral properties, relative to a desired light wavelength(s) is formed over the optical feature. One or more electronic ICs may be bonded to the optical IC to form an integrated package.

公开(公告)号：US12125819B2

公开(公告)日：2024-10-22

申请号：US17883999

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/304 ,  H01L21/306

CPC classification number: H01L24/94 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/76898 ,  H01L24/06 ,  H01L24/33 ,  H01L2224/03845 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/27831 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29005 ,  H01L2224/29011 ,  H01L2224/29016 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/83203 ,  H01L2224/83896 ,  H01L2224/9211 ,  H01L2225/06544

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

公开(公告)号：US20240290823A1

公开(公告)日：2024-08-29

申请号：US18654658

申请日：2024-05-03

Applicant: Taiwan Semiconductor Manufacturing Co,. Ltd.

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01G4/30 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01G4/30 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226

Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.

公开(公告)号：US20240266297A1

公开(公告)日：2024-08-08

申请号：US18602718

申请日：2024-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Hsien-Wei Chen

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/80 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A package includes a redistribution structure, a die package on a first side of the redistribution structure including a first die connected to a second die by metal-to-metal bonding and dielectric-to-dielectric bonding, a dielectric material over the first die and the second die and surrounding the first die, and a first through via extending through the dielectric material and connected to the first die and a first via of the redistribution structure, a semiconductor device on the first side of the redistribution structure includes a conductive connector, wherein a second via of the redistribution structure contacts the conductive connector of the semiconductor device, a first molding material on the redistribution structure and surrounding the die package and the semiconductor device, and a package through via extending through the first molding material to contact a third via of the redistribution structure.

公开(公告)号：US20240153899A1

公开(公告)日：2024-05-09

申请号：US18411674

申请日：2024-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Chih-Chia Hu

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H03K19/1776

CPC classification number: H01L24/06 ,  H01L23/49503 ,  H01L23/49827 ,  H03K19/1776

Abstract: A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.

公开(公告)号：US20240105619A1

公开(公告)日：2024-03-28

申请号：US18523553

申请日：2023-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Noor Mohamed Ettuveettil ,  Po-Hsiang Huang ,  Sen-Bor Jan ,  Ming-Fa Chen ,  Chin-Chou Liu ,  Yi-Kan Cheng

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/5226 ,  H01L24/09 ,  H01L2224/08135 ,  H01L2224/08137 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/08147

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.