公开(公告)号：US20100181984A1

公开(公告)日：2010-07-22

申请号：US12749351

申请日：2010-03-29

申请人： Iwao Fukushi ,  Tomoaki Nishi ,  Takashi Noma

发明人： Iwao Fukushi ,  Tomoaki Nishi ,  Takashi Noma

IPC分类号： G05F1/10

CPC分类号： H02M3/1588 ,  H02M1/32 ,  Y02B70/1466

摘要： The switching control circuit comprises a switching control signal generation circuit that detects a change in ripples of the output voltage and-generates a switching control signal for the on/off control of the switching element to make the output voltage follow the target level; an overcurrent state detection circuit that generates a state signal indicating whether the output current is in an overcurrent state where the output current is equal to or greater than a predetermined current; and a delay circuit that delays the state signal for a same predetermined delay time at both of the times when the output current exceeds the predetermined current and when the output current falls below the predetermined current.

摘要翻译： 开关控制电路包括开关控制信号生成电路，其检测输出电压的波动的变化，并生成用于开关元件的开/关控制的开关控制信号，使输出电压达到目标电平; 产生指示输出电流是否处于输出电流等于或大于预定电流的过电流状态的状态信号的过电流状态检测电路; 以及延迟电路，其在输出电流超过预定电流的两个时间和当输出电流低于预定电流时，延迟状态信号相同的预定延迟时间。

公开(公告)号：US07755874B2

公开(公告)日：2010-07-13

申请号：US12016124

申请日：2008-01-17

申请人： Iwao Fukushi ,  Tomoaki Nishi ,  Takashi Noma

发明人： Iwao Fukushi ,  Tomoaki Nishi ,  Takashi Noma

IPC分类号： H02H3/00

CPC分类号： H02M3/1588 ,  H02M1/32 ,  Y02B70/1466

摘要： A self-excited DC-DC converter includes a switching element that chops an input voltage; a smoothing circuit that smoothes the chopped voltage to generate an output voltage; and a switching control circuit. The switching control circuit includes a switching control signal generation circuit that generates a switching control signal for the on/off control of the switching element by comparing a feedback voltage of the output voltage and a comparison voltage; an output correction circuit that adjusts the comparison voltage according to an error between the feedback voltage and the reference voltage and, when the output current is in the overcurrent state, reduces the level of the comparison voltage; an overcurrent protection signal generation circuit that, when the output current is in an overcurrent state, generates an overcurrent protection signal for turning off the switching element regardless of the switching control signal; and a delay circuit that delays the overcurrent protection signal.

摘要翻译： 自激式DC-DC转换器包括切换输入电压的开关元件; 平滑电路，其使所述斩波电压平滑以产生输出电压; 和开关控制电路。 开关控制电路包括切换控制信号生成电路，其通过比较输出电压的反馈电压和比较电压来生成用于开关元件的导通/截止控制的开关控制信号; 输出校正电路，根据反馈电压和参考电压之间的误差调整比较电压，并且当输出电流处于过电流状态时，降低比较电压的电平; 过电流保护信号产生电路，当输出电流处于过电流状态时，不管开关控制信号如何，都产生用于关断开关元件的过电流保护信号; 以及延迟过电流保护信号的延迟电路。

公开(公告)号：US20100096659A1

公开(公告)日：2010-04-22

申请号：US12527990

申请日：2008-01-30

申请人： Takashi Noma

发明人： Takashi Noma

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L33/486 ,  H01L25/167 ,  H01L31/0203 ,  H01L31/153 ,  H01L33/62 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48091 ,  H01L2924/00014

摘要： The invention is directed to providing a smaller semiconductor device having a light emitting element with a low manufacturing cost and a method of manufacturing the same. An adhesive layer 9 and conductive pastes 10a, 10b are selectively applied to a front surface of a semiconductor substrate 6. Then, a light emitting element (a LED die 4) is formed on the semiconductor substrate 6. A P type semiconductor layer 3 is connected to the conductive paste 10a, and an N type semiconductor layer 2 is connected to the conductive paste 10b. The LED die 4 is thus electrically connected to pad electrodes 8a, 8b through the conductive pastes 10a, 10b. Then, a protection layer 12 having openings in the positions corresponding to the pad electrodes 8a, 8b is formed on the semiconductor substrate 6. Electrode connection layers 13 and conductive terminals 14 are then formed on the pad electrodes 8a, 8b, 8c in the openings. The protection layer 12, the semiconductor substrate 6 and so on are then cut along a predetermined dicing line DL and separated into individual dies.

摘要翻译： 本发明旨在提供一种具有低制造成本的发光元件的较小的半导体器件及其制造方法。 粘合剂层9和导电膏体10a，10b选择性地施加到半导体衬底6的前表面。然后，在半导体衬底6上形成发光元件（LED管芯4）.AP型半导体层3被连接 与导电膏10a连接，并且N型半导体层2连接到导电膏10b。 因此，LED管芯4通过导电膏10a，10b电连接到焊盘电极8a，8b。 然后，在半导体基板6上形成具有与焊盘电极8a，8b对应的位置的开口的保护层12.然后，在焊盘电极8a，8b，8c的开口部中形成电极连接层13和导体端子14 。 然后将保护层12，半导体基板6等沿着预定的切割线DL切割并分离成各个模具。

公开(公告)号：US07413931B2

公开(公告)日：2008-08-19

申请号：US11225898

申请日：2005-09-14

申请人： Takashi Noma ,  Kazuo Okada ,  Hiroshi Yamada ,  Masanori Iida

发明人： Takashi Noma ,  Kazuo Okada ,  Hiroshi Yamada ,  Masanori Iida

IPC分类号： H01L21/312

CPC分类号： H01L24/12 ,  H01L21/76898 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/00014

摘要： The invention is directed to improvement of reliability of a chip size package type semiconductor device in a manufacturing method thereof. A support body is formed on a front surface of a semiconductor substrate with a first insulation film therebetween. Then, a part of the semiconductor substrate is selectively etched from its back surface to form an opening, and then a second insulation film is formed on the back surface. Next, the first insulation film and the second insulation film at a bottom of the opening are selectively etched, to expose pad electrodes at the bottom of the opening. Then, a third resist layer is selectively formed on a second insulation film at boundaries between sidewalls and the bottom of the opening on the back surface of the semiconductor substrate. Furthermore, a wiring layer electrically connected with the pad electrodes at the bottom of the opening and extending onto the back surface of the semiconductor substrate is selectively formed corresponding to a predetermined pattern.

摘要翻译： 本发明的目的在于提高芯片尺寸封装型半导体器件的制造方法的可靠性。 在半导体基板的前表面上形成有第一绝缘膜的支撑体。 然后，从其背面选择性地蚀刻半导体衬底的一部分以形成开口，然后在背面形成第二绝缘膜。 接下来，选择性地蚀刻开口底部的第一绝缘膜和第二绝缘膜，以露出开口底部的焊盘电极。 然后，在半导体衬底的背面的开口的侧壁和底部之间的边界处，在第二绝缘膜上选择性地形成第三抗蚀剂层。 此外，根据预定图案选择性地形成与开口底部的焊盘电极电连接并延伸到半导体衬底的背面上的布线层。

公开(公告)号：US20080171421A1

公开(公告)日：2008-07-17

申请号：US12051502

申请日：2008-03-19

申请人： Akira SUZUKI ,  Takashi Noma ,  Hiroyuki Shinogi ,  Yukihiro Takao ,  Shinzo Ishibe ,  Shigeki Otsuka ,  Keiichi Yamaguchi

发明人： Akira SUZUKI ,  Takashi Noma ,  Hiroyuki Shinogi ,  Yukihiro Takao ,  Shinzo Ishibe ,  Shigeki Otsuka ,  Keiichi Yamaguchi

IPC分类号： H01L21/304

CPC分类号： H01L21/78 ,  H01L23/3114 ,  H01L23/482 ,  H01L23/49827 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2224/05599 ,  H01L2224/05099

摘要： Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.

摘要翻译： CSP型半导体器件降低成本并提高可靠性。 作为支撑板的玻璃基板通过粘合剂粘合到其上形成有第一布线的半导体晶片的第一表面。 半导体晶片的厚度通过在与半导体晶片的第一表面相对的半导体晶片的第二表面上的背面研磨半导体晶片来减少。 湿式蚀刻半导体晶片以去除在后研磨期间引起的半导体晶片的第二表面上的凸起和凹陷。 然后蚀刻半导体晶片的第二表面以形成锥形槽。 湿式蚀刻半导体晶片以减少由蚀刻引起的凸起和凹陷，并且绕着凹槽的一角。 湿蚀刻提高了绝缘膜，布线和保护膜的覆盖率，并提高了半导体器件的产量和可靠性。

公开(公告)号：US07399683B2

公开(公告)日：2008-07-15

申请号：US11035399

申请日：2005-01-14

申请人： Takashi Noma ,  Hiroyuki Shinogi ,  Yukihiro Takao

发明人： Takashi Noma ,  Hiroyuki Shinogi ,  Yukihiro Takao

IPC分类号： H01L21/00

CPC分类号： H01L24/12 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/12044

摘要： A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate.

摘要翻译： 本发明的半导体器件的制造方法包括通过第一氧化膜在Si衬底上形成金属焊盘，将Si衬底和支撑衬底接合，通过接合膜固定Si衬底，通过蚀刻Si衬底形成开口 然后在Si衬底的后表面和开口中形成第二氧化物膜，在蚀刻第二氧化膜之后形成连接到金属焊盘的布线，在布线上形成导电端子，从导电端子的背面切割 Si衬底到所述接合膜并分离所述Si衬底和所述保持衬底。

公开(公告)号：US07371693B2

公开(公告)日：2008-05-13

申请号：US10784888

申请日：2004-02-24

申请人： Akira Suzuki ,  Takashi Noma ,  Hiroyuki Shinogi ,  Yukihiro Takao ,  Shinzo Ishibe ,  Shigeki Otsuka ,  Keiichi Yamaguchi

发明人： Akira Suzuki ,  Takashi Noma ,  Hiroyuki Shinogi ,  Yukihiro Takao ,  Shinzo Ishibe ,  Shigeki Otsuka ,  Keiichi Yamaguchi

IPC分类号： H01L21/461

CPC分类号： H01L21/78 ,  H01L23/3114 ,  H01L23/482 ,  H01L23/49827 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2224/05599 ,  H01L2224/05099

摘要： Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.

摘要翻译： CSP型半导体器件降低成本并提高可靠性。 作为支撑板的玻璃基板通过粘合剂粘合到其上形成有第一布线的半导体晶片的第一表面。 半导体晶片的厚度通过在与半导体晶片的第一表面相对的半导体晶片的第二表面上的背面研磨半导体晶片来减少。 湿式蚀刻半导体晶片以去除在后研磨期间引起的半导体晶片的第二表面上的凸起和凹陷。 然后蚀刻半导体晶片的第二表面以形成锥形槽。 湿式蚀刻半导体晶片以减少由蚀刻引起的凸起和凹陷，并且绕着凹槽的一角。 湿蚀刻提高了绝缘膜，布线和保护膜的覆盖率，并提高了半导体器件的产量和可靠性。

公开(公告)号：US07312521B2

公开(公告)日：2007-12-25

申请号：US10420943

申请日：2003-04-23

申请人： Takashi Noma ,  Hiroyuki Shinogi ,  Nobuyuki Takai ,  Katsuhiko Kitagawa ,  Ryoji Tokushige ,  Takayasu Otagaki ,  Tatsuya Ando ,  Mitsuru Okigawa

发明人： Takashi Noma ,  Hiroyuki Shinogi ,  Nobuyuki Takai ,  Katsuhiko Kitagawa ,  Ryoji Tokushige ,  Takayasu Otagaki ,  Tatsuya Ando ,  Mitsuru Okigawa

IPC分类号： H01L23/48 ,  H01L23/12 ,  H01L29/70 ,  H01L31/02 ,  H01L23/04

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

摘要翻译： 具有球形导电端子的BGA（球栅阵列）型半导体器件降低了成本并提高了可靠性。 第一布线形成在形成在半导体管芯的表面上的绝缘膜上。 在半导体管芯的表面上接合玻璃基板，半导体管芯的侧表面和背面被绝缘膜覆盖。 第二布线连接到第一布线的侧表面或后表面并在半导体管芯的后表面上延伸。 导电端子如凸块形成在第二布线上。

公开(公告)号：US07304463B2

公开(公告)日：2007-12-04

申请号：US11115754

申请日：2005-04-27

申请人： Takashi Noma

发明人： Takashi Noma

IPC分类号： G05F1/618 ,  G05F1/575

CPC分类号： H02M3/1588 ,  Y02B70/1466

摘要： A DC-DC converter includes an Nch FET1 which is series connected between an input terminal and an output terminal, and an Nch FET2 which is connected between the output terminal side of the Nch FET1 and a ground terminal. On the output terminal side of the circuits, a smoothing circuit and a comparator circuit are connected. The output side of the comparator circuit is connected to an on-time limiter circuit, and the on-time limiter circuit is connected to an H/S driver circuit for controlling the Nch FET1 through an inverter and directly connected to an L/S driver circuit for controlling the Nch FET2. Here, when a switching control signal for turning on the Nch FET1 is input to the on-time limiter circuit from the comparator, the on-time limiter circuit detects a time in the on state and outputs a signal by which the Nch FET1 is temporarily off controlled.

摘要翻译： DC-DC转换器包括串联连接在输入端子和输出端子之间的Nch FET <1>和连接在输出端子侧之间的Nch FET <2> 的Nch FET 1＆lt; 1＆gt;和接地端子。 在电路的输出端侧连接有平滑电路和比较电路。 比较器电路的输出侧与导通时间限制电路连接，接通时间限制电路通过逆变器连接到H / S驱动电路，以控制Nch FET <1> 直接连接到用于控制Nch FET <2>的L / S驱动电路。 这里，当用于接通Nch FET <1>的开关控制信号从比较器输入到接通时间限制器电路时，接通时间限制器电路检测处于导通状态的时间，并输出 Nch FET 1暂时关闭的信号被控制。

公开(公告)号：US07256073B2

公开(公告)日：2007-08-14

申请号：US11492044

申请日：2006-07-25

申请人： Takashi Noma ,  Akira Suzuki ,  Hiroyuki Shinogi

发明人： Takashi Noma ,  Akira Suzuki ,  Hiroyuki Shinogi

IPC分类号： H01L21/00

CPC分类号： H01L24/02 ,  H01L21/76898 ,  H01L23/3114 ,  H01L25/0657 ,  H01L27/14806 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06565 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00

摘要： A stacked MCM is manufactured at reduced cost without using expensive apparatus. A first wiring and a second wiring are formed on a surface of a semiconductor chip of a first semiconductor device through an insulation film. A glass substrate having an opening to expose the second wiring is bonded to the surface of the semiconductor chip on which the first wiring and the second wiring are formed. A third wiring is disposed on a back surface and a side surface of the semiconductor chip through an insulation film and connected to the first wiring. And a conductive terminal of another semiconductor device is connected to the second wiring through the opening.

摘要翻译： 在不使用昂贵的设备的情况下，以低成本制造堆叠MCM。 通过绝缘膜在第一半导体器件的半导体芯片的表面上形成第一布线和第二布线。 具有露出第二布线的开口的玻璃基板被接合到形成有第一布线和第二布线的半导体芯片的表面上。 第三布线通过绝缘膜设置在半导体芯片的背面和侧面上并连接到第一布线。 并且另一半导体器件的导电端子通过开口连接到第二布线。