公开(公告)号：US08105856B2

公开(公告)日：2012-01-31

申请号：US10876532

申请日：2004-06-28

Applicant: Takashi Noma ,  Hiroyuki Shinogi ,  Nobuyuki Takai ,  Katsuhiko Kitagawa ,  Ryoji Tokushige ,  Takayasu Otagaki ,  Tatsuya Ando ,  Mitsuru Okigawa

Inventor： Takashi Noma ,  Hiroyuki Shinogi ,  Nobuyuki Takai ,  Katsuhiko Kitagawa ,  Ryoji Tokushige ,  Takayasu Otagaki ,  Tatsuya Ando ,  Mitsuru Okigawa

IPC: H01L21/00

CPC classification number: H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

Abstract translation: 具有球形导电端子的BGA（球栅阵列）型半导体器件降低了成本并提高了可靠性。 第一布线形成在形成在半导体管芯的表面上的绝缘膜上。 在半导体管芯的表面上接合玻璃基板，半导体管芯的侧表面和背面被绝缘膜覆盖。 第二布线连接到第一布线的侧表面或后表面并在半导体管芯的后表面上延伸。 导电端子如凸块形成在第二布线上。

公开(公告)号：US20060033198A1

公开(公告)日：2006-02-16

申请号：US11206146

申请日：2005-08-18

Applicant: Takashi Noma ,  Hiroyuki Shinogi ,  Nobuyuki Takai ,  Katsuhiko Kitagawa ,  Ryoji Tokushige ,  Takayasu Otagaki ,  Tatsuya Ando ,  Mitsuru Okigawa

Inventor： Takashi Noma ,  Hiroyuki Shinogi ,  Nobuyuki Takai ,  Katsuhiko Kitagawa ,  Ryoji Tokushige ,  Takayasu Otagaki ,  Tatsuya Ando ,  Mitsuru Okigawa

IPC: H01L23/04

CPC classification number: H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

Abstract translation: 具有球形导电端子的BGA（球栅阵列）型半导体器件降低了成本并提高了可靠性。 第一布线形成在形成在半导体管芯的表面上的绝缘膜上。 在半导体管芯的表面上接合玻璃基板，半导体管芯的侧表面和背面被绝缘膜覆盖。 第二布线连接到第一布线的侧表面或后表面并在半导体管芯的后表面上延伸。 导电端子如凸块形成在第二布线上。

公开(公告)号：US06534387B1

公开(公告)日：2003-03-18

申请号：US09680613

申请日：2000-10-06

Applicant: Hiroyuki Shinogi ,  Ryoji Tokushige ,  Nobuyuki Takai

Inventor： Hiroyuki Shinogi ,  Ryoji Tokushige ,  Nobuyuki Takai

IPC: H01L21301

CPC classification number: H01L21/78 ,  H01L21/56 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00014

Abstract: After a metal post 8 is formed on a semiconductor wafer 20, a groove 21 is formed in a first dicing step. The semiconductor wafer is resin-sealed by a rein layer R from its upper surface. The semiconductor wafer is ground from its lower surface to a depth reaching the bottom of the groove 21 so that the semiconductor wafer is divided into individual chips 20A. The resin layer is ground to expose the head of the metal post. After a solder ball is loaded on the metal post 8, the portion of the resin layer between adjacent chips 20A is diced in a second dicing step so that the individual chips 20A are separated from one another.

Abstract translation: 在半导体晶片20上形成金属柱8之后，在第一切割步骤中形成凹槽21。 半导体晶片从其上表面被树脂层R树脂密封。 将半导体晶片从其下表面研磨到达凹槽21的底部的深度，使得半导体晶片被分成单独的芯片20A。 研磨树脂层以暴露金属柱的头部。 在金属柱8上装载焊球后，在第二切割步骤中切割相邻芯片20A之间的树脂层的部分，使得各个芯片20A彼此分离。

公开(公告)号：US06656758B1

公开(公告)日：2003-12-02

申请号：US09684604

申请日：2000-10-06

Applicant: Hiroyuki Shinogi ,  Ryoji Tokushige ,  Nobuyuki Takai

Inventor： Hiroyuki Shinogi ,  Ryoji Tokushige ,  Nobuyuki Takai

IPC: H01L2100

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014

Abstract: First, a passivation film 3 having an opening K from which a part of the Al electrode 1 formed through an interlayer insulating film 2 made of a BPSG film is exposed is formed on a wafer. A wiring layer 7, which is connected to the Al electrode 1 exposed from the opening K and extended to the upper surface of the wafer, is formed. After a metal post 8 is formed on the wiring layer 7, a first groove TC1, which is located on the periphery of the chip inclusive of the wiring layer 7 and half cuts the wafer, is formed. The upper portion of the interlayer insulating film 2 is isotropically etched through the first groove TC1 to form a second groove TC2 having a larger opening diameter than that of the first groove TC1. The wafer surface inclusive of the wiring layer 7, second groove TC2 and first groove TC1 is resin-sealed to form an insulating resin layer R. Thereafter, a solder ball 12 is formed on the metal post 8 exposed from the insulating resin layer R. Finally, the wafer is fully cut through the insulating resin layer R formed in the first and the second grooves TC1 and TC2.

Abstract translation: 首先，在晶片上形成具有通过由BPSG膜构成的层间绝缘膜2而形成的Al电极1的一部分露出的开口K的钝化膜3。 形成与从开口K露出并延伸到晶片的上表面的Al电极1连接的布线层7。 在布线层7上形成金属柱8之后，形成位于包括布线层7在内的芯片周边的第一沟槽TC1，并切割半晶片。 层间绝缘膜2的上部通过第一沟槽TC1进行各向同性蚀刻，以形成具有比第一沟槽TC1的开口直径大的开口直径的第二沟槽TC2。 包括布线层7，第二沟槽TC2和第一沟槽TC1的晶片表面被树脂密封以形成绝缘树脂层R.之后，在暴露于绝缘树脂层R的金属柱8上形成焊球12。 最后，通过形成在第一和第二槽TC1和TC2中的绝缘树脂层R，完全切割晶片。

公开(公告)号：US06326701B1

公开(公告)日：2001-12-04

申请号：US09512481

申请日：2000-02-23

Applicant: Hiroyuki Shinogi ,  Nobuyuki Takai ,  Ryoji Tokushige ,  Yukihiro Takao ,  Katsuhiko Kitagawa

Inventor： Hiroyuki Shinogi ,  Nobuyuki Takai ,  Ryoji Tokushige ,  Yukihiro Takao ,  Katsuhiko Kitagawa

IPC: H01L2176

CPC classification number: H01L23/3114 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05569 ,  H01L2224/0558 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2224/05552

Abstract: A removal area EL is provided as a first dicing line in a dicing area, coat materials 6′ and 7′ are put on the flanks of the removal area, a resin layer R is formed, and a dicing blade narrower than the width of the removal area EL is used to fully cut on a second dicing line, whereby the interface exposed by the first dicing can be coated and protected.

Abstract translation: 在切割区域中设置去除区域EL作为第一切割线，将涂层材料6'和7'放置在去除区域的侧面上，形成树脂层R，并且切割刀片的宽度比 去除区域EL用于在第二切割线上完全切割，由此通过第一切割暴露的界面可被涂覆和保护。

公开(公告)号：US07312521B2

公开(公告)日：2007-12-25

申请号：US10420943

申请日：2003-04-23

Applicant: Takashi Noma ,  Hiroyuki Shinogi ,  Nobuyuki Takai ,  Katsuhiko Kitagawa ,  Ryoji Tokushige ,  Takayasu Otagaki ,  Tatsuya Ando ,  Mitsuru Okigawa

Inventor： Takashi Noma ,  Hiroyuki Shinogi ,  Nobuyuki Takai ,  Katsuhiko Kitagawa ,  Ryoji Tokushige ,  Takayasu Otagaki ,  Tatsuya Ando ,  Mitsuru Okigawa

IPC: H01L23/48 ,  H01L23/12 ,  H01L29/70 ,  H01L31/02 ,  H01L23/04

CPC classification number: H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

Abstract translation: 具有球形导电端子的BGA（球栅阵列）型半导体器件降低了成本并提高了可靠性。 第一布线形成在形成在半导体管芯的表面上的绝缘膜上。 在半导体管芯的表面上接合玻璃基板，半导体管芯的侧表面和背面被绝缘膜覆盖。 第二布线连接到第一布线的侧表面或后表面并在半导体管芯的后表面上延伸。 导电端子如凸块形成在第二布线上。

公开(公告)号：US06424051B1

公开(公告)日：2002-07-23

申请号：US09500271

申请日：2000-02-08

Applicant: Hiroyuki Shinogi ,  Nobuyuki Takai ,  Ryoji Tokushige ,  Katsuhiko Kitagawa

Inventor： Hiroyuki Shinogi ,  Nobuyuki Takai ,  Ryoji Tokushige ,  Katsuhiko Kitagawa

IPC: H01L2328

CPC classification number: H01L23/564 ,  H01L23/3185 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To improve the moisture resistance of a chip size package, a seal ring 4 is made up of tungsten plugs and metal electrodes 11 and 12. Further, a spacer is formed on both or either of a first flank 13 and a second flank 14. The spacer can be formed on all interlayer insulating films extended to a dicing line part 3, whereby multiple seal rings can be provided.

Abstract translation: 为了提高芯片尺寸封装的耐湿性，密封环4由钨插头和金属电极11和12组成。此外，在第一侧面13和第二侧面14两者上形成间隔件。 可以在延伸到切割线部分3的所有层间绝缘膜上形成间隔物，从而可以提供多个密封环。

公开(公告)号：US06329288B1

公开(公告)日：2001-12-11

申请号：US09489709

申请日：2000-01-24

Applicant: Ryoji Tokushige ,  Nobuyuki Takai ,  Hiroyuki Shinogi ,  Yukihiro Takao

Inventor： Ryoji Tokushige ,  Nobuyuki Takai ,  Hiroyuki Shinogi ,  Yukihiro Takao

IPC: H01L2144

CPC classification number: H01L24/12 ,  H01L21/56 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A process of exposing the head of a metal post used with a chip size package is simplified. A first semiconductor manufacturing method comprising the steps of forming an insulating resin layer R so as to completely cover the top of a metal post 8 and then polishing the resin layer so as to expose the head of the metal post, and a second semiconductor manufacturing method comprising the steps of forming an insulating resin layer R so as to completely cover the top of the metal post 8, then back grinding the wafer rear face, and then polishing the resin layer R so as to expose the head of the metal post are provided.

Abstract translation: 使用与芯片尺寸封装件一起使用的金属柱头的曝光过程被简化。 第一半导体制造方法包括以下步骤：形成绝缘树脂层R，以完全覆盖金属柱8的顶部，然后抛光树脂层以暴露金属柱的头部;以及第二半导体制造方法 包括以下步骤：形成绝缘树脂层R，以完全覆盖金属柱8的顶部，然后对晶片背面进行背面磨削，然后对树脂层R进行抛光以使金属柱的头部露出 。

公开(公告)号：US07880256B2

公开(公告)日：2011-02-01

申请号：US11386106

申请日：2006-03-22

Applicant: Nobuyuki Takai ,  Takuya Suzuki ,  Yuji Tsukada

Inventor： Nobuyuki Takai ,  Takuya Suzuki ,  Yuji Tsukada

IPC: H01L29/40 ,  H01L21/4763 ,  H01L21/70

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05138 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/48463 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015

Abstract: The invention provides a semiconductor device with a bonding pad made of a wiring layer including aluminum and its manufacturing method that enhance the yield of the semiconductor device. The method of manufacturing the semiconductor device of the invention includes removing a portion of an antireflection layer (e.g. made of a titanium alloy) formed on an uppermost second wiring layer (e.g. made of aluminum) on a semiconductor substrate by etching, forming a passivation layer covering the antireflection layer and a portion of the second wiring layer where the antireflection layer is not formed and having an opening exposing the other portion of the second wiring layer, and dividing the semiconductor substrate into a plurality of semiconductor dice by dicing. These processes can prevent the antireflection layer from being exposed in the opening, and this can prevent a component of the second wiring layer from being eluted due to cell reaction between the second wiring layer and the antireflection layer as has been seen in the conventional art.

Abstract translation: 本发明提供一种半导体器件，其具有由包括铝的布线层制成的焊盘及其制造方法，其提高半导体器件的产量。 制造本发明的半导体器件的方法包括通过蚀刻在半导体衬底上去除形成在最上层的第二布线层（例如由铝制成的）的抗反射层（例如由钛合金制成）的一部分，形成钝化层 覆盖防反射层和第二布线层的不形成防反射层的部分，并且具有暴露第二布线层的另一部分的开口，并且通过切割将半导体基板分割成多个半导体管芯。 这些处理可以防止防反射层暴露在开口中，并且这可以防止第二布线层的部件由于第二布线层和抗反射层之间的电池反应而被洗脱，如在现有技术中已经看到的那样。

公开(公告)号：US06555459B1

公开(公告)日：2003-04-29

申请号：US09491033

申请日：2000-01-25

Applicant: Ryoji Tokushige ,  Nobuyuki Takai ,  Hiroyuki Shinogi ,  Seiichi Ono

Inventor： Ryoji Tokushige ,  Nobuyuki Takai ,  Hiroyuki Shinogi ,  Seiichi Ono

IPC: H01L2100

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/051 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01083

Abstract: A metal post used with a chip size package and barrier metal formed on the metal post are omitted. After a second opening where a wiring layer is exposed is made, a second seed layer is formed and a solder post 7 is formed with the seed layer as a plate electrode.

Abstract translation: 省略了在金属柱上形成的具有芯片尺寸封装和阻挡金属的金属柱。 在布线层暴露的第二开口之后，形成第二种子层，并且形成具有种子层作为平板电极的焊料柱7。