公开(公告)号：US06335887B1

公开(公告)日：2002-01-01

申请号：US09727544

申请日：2000-12-04

申请人： Shigekazu Aoki ,  Seiji Sawada ,  Mikio Asakura ,  Takeshi Hamamoto ,  Masakazu Hirose

发明人： Shigekazu Aoki ,  Seiji Sawada ,  Mikio Asakura ,  Takeshi Hamamoto ,  Masakazu Hirose

IPC分类号： G11C700

CPC分类号： G11C29/34

摘要： The semiconductor memory device has a word configuration determination signal generating circuit including a plurality of generating circuits, each of which is formed of two clocked inverters and two inverters. In a normal operation mode, a test mode signal TX4 is inactivated and a word configuration determination signal [x16E] of an H level is output. In a test mode, the test mode signal TX4 is activated and a word configuration determination signal [x4E] of an H level is output. Thus, in the test mode, the word configuration is switched to the one that is smaller than in the normal operation mode. This allows simultaneous testing of a larger number of semiconductor memory devices.

公开(公告)号：US06288956B1

公开(公告)日：2001-09-11

申请号：US09477717

申请日：2000-01-05

申请人： Tetsushi Tanizaki ,  Tetsuo Kato ,  Mikio Asakura ,  Yasuhiro Konishi ,  Takayuki Miyamoto

发明人： Tetsushi Tanizaki ,  Tetsuo Kato ,  Mikio Asakura ,  Yasuhiro Konishi ,  Takayuki Miyamoto

IPC分类号： G11C1140

CPC分类号： G11C29/46

摘要： A semiconductor device according to the present invention includes a plurality of test mode circuits. Each test mode circuit includes a plurality of decode circuits decoding an input signal and a plurality of latch circuits. Each decode circuit generates a test mode signal. The test mode signals are held in the latch circuits. Each test mode circuit further includes decode circuits outputting a group reset signal for resetting a corresponding latch circuit. Thus, a plurality of test mode signals can be combined arbitrarily and serially.

摘要翻译： 根据本发明的半导体器件包括多个测试模式电路。 每个测试模式电路包括解码输入信号和多个锁存电路的多个解码电路。 每个解码电路产生测试模式信号。 测试模式信号保持在锁存电路中。 每个测试模式电路还包括输出用于复位相应的锁存电路的组复位信号的解码电路。 因此，多个测试模式信号可以任意和连续地组合。

公开(公告)号：US06272055B1

公开(公告)日：2001-08-07

申请号：US09168962

申请日：1998-10-09

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：US6002621A

公开(公告)日：1999-12-14

申请号：US33657

申请日：1998-03-03

申请人： Shinji Tanaka ,  Koji Tanaka ,  Mikio Asakura ,  Kenichi Yasuda

发明人： Shinji Tanaka ,  Koji Tanaka ,  Mikio Asakura ,  Kenichi Yasuda

IPC分类号： G11C29/24 ,  G11C7/00

CPC分类号： G11C29/24

摘要： Normal column selection signal switching device (20) is provided to switch a signal outputted from normal column selection signal generating device (19) in response to a test-mode signal (TMC1). Even if the normal column selection signal generating device (19) outputs a signal to disable a normal column decoder (3), the normal column selection signal switching device (20) switches the signal to enable the normal column decoder (3) to operate in the test operation. Having this configuration, a semiconductor memory device enables writing of data into all the normal memory cells even after some of the normal memory cells are replaced by spare memory cells.

摘要翻译： 提供正常列选择信号切换装置（20）以响应于测试模式信号（TMC1）切换从正常列选择信号发生装置（19）输出的信号。 即使正常列选择信号生成装置（19）输出禁止通常的列解码器（3）的信号，通常的列选择信号切换装置（20）切换信号，使通常的列解码器（3）能够工作 测试操作。 具有这种配置，半导体存储器件即使在由备用存储器单元代替一些正常存储器单元之后，也能够将数据写入所有正常存储单元。

公开(公告)号：US5973554A

公开(公告)日：1999-10-26

申请号：US055779

申请日：1998-04-07

申请人： Kyoji Yamasaki ,  Mikio Asakura ,  Tadaaki Yamauchi

发明人： Kyoji Yamasaki ,  Mikio Asakura ,  Tadaaki Yamauchi

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C11/407 ,  H01L21/8242 ,  H01L23/50 ,  H01L27/02 ,  H01L27/108 ,  H01L25/00

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L24/49 ,  H01L27/0218 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/3011

摘要： A semiconductor device comprises an MOS transistor, as a capacitive element, formed at the surface of a semiconductor substrate. A first power supply interconnection, above the substrate, applies a first power supply potential to the source and drain of the transistor. A second power supply interconnection, above the first interconnection, applies a second potential to the gate of the transistor. A third power supply interconnection is formed above, in parallel with and connected to the second power supply interconnection. An externally sourced potential is down-converted to be applied appropriately to the first, second and third power supply interconnections. This configuration achieves a semiconductor device that is less susceptible to power supply noise.

公开(公告)号：US5972756A

公开(公告)日：1999-10-26

申请号：US908000

申请日：1997-08-11

申请人： Takashi Kono ,  Mikio Asakura ,  Hideto Hidaka ,  Kenichi Yasuda

发明人： Takashi Kono ,  Mikio Asakura ,  Hideto Hidaka ,  Kenichi Yasuda

IPC分类号： H01L21/82 ,  H01L21/02 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/108 ,  H01S3/00

CPC分类号： H01L23/5258 ,  H01L27/10844 ,  H01L28/91 ,  H01L2924/0002

摘要： In a method of fabricating a semiconductor device, an interlayer insulating film is selectively etched to remove a level difference at an area of the interlayer insulating film on a cell plate on cylindrical capacitors and simultaneously form a concave portion on a fuse portion. Since the etching is ended to a degree that the cell plate is not exposed, the concave portion can be formed on the fuse portion not exposed. This does not add a step of forming a protection film on the fuse portion.

摘要翻译： 在制造半导体器件的方法中，选择性地蚀刻层间绝缘膜以消除圆柱形电容器上的单元板上的层间绝缘膜的区域处的电平差，同时在熔丝部分上形成凹部。 由于蚀刻结束到单元板不暴露的程度，凹部可以形成在未露出的熔丝部上。 这不会在保险丝部分上增加形成保护膜的步骤。

公开(公告)号：US5943273A

公开(公告)日：1999-08-24

申请号：US899143

申请日：1997-07-23

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C11/4091 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

公开(公告)号：US5875145A

公开(公告)日：1999-02-23

申请号：US795529

申请日：1997-02-05

申请人： Kyoji Yamasaki ,  Tadaaki Yamauchi ,  Mikio Asakura

发明人： Kyoji Yamasaki ,  Tadaaki Yamauchi ,  Mikio Asakura

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C1/34

CPC分类号： G11C5/147

摘要： A semiconductor memory device includes a memory cell array, peripheral circuits including a column decoder for connecting a word line, and a VDC circuit for peripherals, for generating an internal power supply voltage based on an external power supply voltage. VDC circuit for peripherals supplies the internal power supply voltage to peripheral circuits including the column decoder, other than the sense amplifier, output buffer and internal initial stage. The supplying capability of the VDC circuit for peripherals is increased in response to a VDCE signal which is output from a clock generation circuit when column decoder is activated. Therefore, even when power consumption in the peripheral circuit is increased as the column decoder is activated, sufficient power can be supplied to the peripheral circuit.

摘要翻译： 半导体存储器件包括存储单元阵列，包括用于连接字线的列解码器和用于外围设备的VDC电路的外围电路，用于基于外部电源电压产生内部电源电压。 用于外设的VDC电路将内部电源电压提供给除了读出放大器，输出缓冲器和内部初始级之外的列解码器的外围电路。 响应于当列解码器被激活时从时钟发生电路输出的VDCE信号，外围设备的VDC电路的供应能力增加。 因此，即使当列解码器被激活时外围电路的功率消耗增加，也可以向外围电路提供足够的电力。

公开(公告)号：US5844767A

公开(公告)日：1998-12-01

申请号：US675760

申请日：1996-07-03

申请人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

发明人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： H01L29/40 ,  G11C5/14 ,  G11C7/10 ,  G11C11/407 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0944 ,  G11C13/00

CPC分类号： G11C7/1078 ,  G11C5/145 ,  G11C5/146 ,  G11C5/147

摘要： The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting circuit includes two NMOS transistor connected to a ground node. The level shift circuits include two PMOS transistors and two NMOS transistors. Before a through current flows between the node having the boosted potential Vpp and the ground node, any of the transistor included in the first current cutting circuit and any of the transistors included in the second current cutting circuits are turned off. Therefore, through current between the node having the boosted potential Vbb and the ground node can be prevented.

摘要翻译： 电平转换电路包括第一电流切断电路，第二电流切断电路，电平移位电路和反相器。 第一电流切割电路包括连接到具有升压电位Vpp的节点的两个PMOS晶体管。 第二电流切断电路包括连接到接地节点的两个NMOS晶体管。 电平移位电路包括两个PMOS晶体管和两个NMOS晶体管。 在直流电流在具有升压电位Vpp的节点和接地节点之间流动之前，包括在第一电流切割电路中的任何晶体管和包括在第二电流切割电路中的任何晶体管都被截止。 因此，可以防止具有升压电位Vbb的节点与接地节点之间的电流。

公开(公告)号：US5828258A

公开(公告)日：1998-10-27

申请号：US639326

申请日：1996-04-25

申请人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

发明人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： G11C11/403 ,  G06F1/04 ,  G06F1/08 ,  G11C11/401 ,  G11C11/406 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50

CPC分类号： G11C29/028 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C11/401

摘要： A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied.