公开(公告)号：US08854067B2

公开(公告)日：2014-10-07

申请号：US13594292

申请日：2012-08-24

Applicant: Amol Joshi ,  Charlene Chen ,  John Foster ,  Zhendong Hong ,  Olov Karlsson ,  Bei Li ,  Dipankar Pramanik ,  Usha Raghuram ,  Mark Victor Raymond ,  Jingang Su ,  Bin Yang

Inventor： Amol Joshi ,  Charlene Chen ,  John Foster ,  Zhendong Hong ,  Olov Karlsson ,  Bei Li ,  Dipankar Pramanik ,  Usha Raghuram ,  Mark Victor Raymond ,  Jingang Su ,  Bin Yang

IPC: G01R27/08 ,  G01R31/28

CPC classification number: G01R27/08 ,  G01R31/2831 ,  H01L22/14 ,  H01L22/20

Abstract: Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Abstract translation: 描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。 还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

公开(公告)号：US20140188417A1

公开(公告)日：2014-07-03

申请号：US13877317

申请日：2011-10-13

Applicant: Xiuzhen Dong ,  Xuyang Huo ,  Fusheng You ,  Xuetao Shi ,  Feng Fu ,  Ruigang Liu ,  Zhenyu Ji ,  Canhua Xu ,  Bin Yang ,  Min Yang ,  Jiaxue Qi ,  Wen Zhang ,  Nan Wang

Inventor： Xiuzhen Dong ,  Xuyang Huo ,  Fusheng You ,  Xuetao Shi ,  Feng Fu ,  Ruigang Liu ,  Zhenyu Ji ,  Canhua Xu ,  Bin Yang ,  Min Yang ,  Jiaxue Qi ,  Wen Zhang ,  Nan Wang

IPC: G01R27/02

CPC classification number: G01R27/02 ,  A61B5/053 ,  A61B5/0536 ,  A61B5/7225 ,  G01R27/14

Abstract: An electrical impedance detecting device of a portable electrical impedance imaging system by utilizing a theory of sending excitation signal and detecting response signal and a method thereof, wherein the excitation signal is a constant square wave excitation current signal, the response voltage signal on a target is transformed to a square wave signal with appropriate amplitudes by buffering, amplifying, RC filtering and differential amplifying circuits, and then is transformed to a digital signal at a proper time by an analog-to-digital converter. The response voltage signal is sampled once when at high level and once when at low level for every circle of the square wave signal by the ADC, and a sample V1 and a sample V2 are obtained respectively, difference of the sample V1 and the sample V2 is taken as a detecting result for one circle. An average value of the detecting result from a plurality of circles may be taken as a final result. Information of electrical impedance is illustrated by the final result because the excitation current signal is constant.

Abstract translation: 一种通过利用发送激励信号和检测响应信号的理论的便携式电阻抗成像系统的电阻抗检测装置及其方法，其中激励信号是恒定方波激励电流信号，目标上的响应电压信号是 通过缓冲，放大，RC滤波和差分放大电路转换成具有适当幅度的方波信号，然后通过模拟 - 数字转换器在适当的时间转换为数字信号。 响应电压信号在高电平时被采样一次，一旦在ADC的每个圆波信号的低电平处被采样一次，并且分别获得样本V1和样本V2，样本V1和样本V2的差 作为一个圆的检测结果。 可以将来自多个圆的检测结果的平均值作为最终结果。 由于激励电流信号是恒定的，所以最终结果说明了电阻抗的信息。

公开(公告)号：US20140132992A1

公开(公告)日：2014-05-15

申请号：US14128351

申请日：2012-05-18

Applicant: Haifeng Li ,  Bin Yang

Inventor： Haifeng Li ,  Bin Yang

IPC: G06K15/02

CPC classification number: G06K15/1881 ,  H04N1/40087 ,  H04N1/4055

Abstract: The present application discloses a method and an apparatus for generating multi-bit depth halftone amplitude-modulation dots. The method may comprise: scanning an input image to obtain a value of a current pixel Pxy, where x represents a lateral position index of the current pixel, and y represents a vertical position index of the current pixel; obtaining gj from a preset multi-bit depth threshold matrix G by starting with i=0, and determining if Pxy

Abstract translation: 本申请公开了一种用于产生多位深度半色调幅度调制点的方法和装置。 该方法可以包括：扫描输入图像以获得当前像素Pxy的值，其中x表示当前像素的横向位置索引，y表示当前像素的垂直位置索引; 通过以i = 0开始从预设的多位深度阈值矩阵G获得gj，并且确定Pxy

公开(公告)号：US08680624B2

公开(公告)日：2014-03-25

申请号：US13488109

申请日：2012-06-04

Applicant: Man Fai Ng ,  Bin Yang

Inventor： Man Fai Ng ,  Bin Yang

IPC: H01L21/70 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/84 ,  H01L21/76267 ,  H01L21/823878 ,  H01L29/66772

Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.

Abstract translation: 提供了用于制造在绝缘材料区域内具有阻挡区域的半导体器件的方法和装置，导致从绝缘材料区域的脱气路径。 一种方法包括在靠近半导体材料的隔离区域的绝缘材料内形成阻挡区域，并形成覆盖半导体材料的隔离区域的栅极结构。 阻挡区域与半导体材料的隔离区域相邻，导致绝缘材料内的除气路径。

公开(公告)号：US08658530B2

公开(公告)日：2014-02-25

申请号：US13612240

申请日：2012-09-12

Applicant: Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

Inventor： Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

IPC: H01L21/4763 ,  H01L21/477 ,  H01L21/36

CPC classification number: H01L29/7839 ,  H01L21/28052 ,  H01L21/28537 ,  H01L29/47 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/66772 ,  H01L29/78618

Abstract: An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.

Abstract translation: 提供了在高温下基本上未附聚的外延Ni硅化物膜，以及形成外延Ni硅化物膜的方法。 本公开的Ni硅化物膜特别可用于形成ETSOI（极薄的绝缘体上硅）肖特基结源极/漏极FET。 得到的外延Ni硅化物膜具有改善的热稳定性，并且在高温下不聚结。

公开(公告)号：US20140038402A1

公开(公告)日：2014-02-06

申请号：US13563202

申请日：2012-07-31

Applicant: Andy C. Wei ,  Bin Yang ,  Francis M. Tambwe

Inventor： Andy C. Wei ,  Bin Yang ,  Francis M. Tambwe

IPC: H01L21/336 ,  H01L21/311

CPC classification number: H01L27/11 ,  H01L21/823821 ,  H01L29/7843

Abstract: A method for fabricating a dual-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the FinFET structure. The method further includes depositing a second workfunction material in a layer in a plurality of trenches of the portion and depositing a stress material layer over the second workfunction material layer.

Abstract translation: 一种用于制造双功函数FinFET结构的方法，包括在FinFET结构的多个沟槽中的层中沉积第一功函数材料，在第一功函数材料层上沉积低电阻材料层，以及蚀刻低电阻材料 层和来自FinFET结构的一部分的第一功函数材料层。 该方法还包括在该部分的多个沟槽中的层中沉积第二功函数材料，并在第二功函数材料层上沉积应力材料层。

公开(公告)号：US08580541B2

公开(公告)日：2013-11-12

申请号：US12962366

申请日：2010-12-07

Applicant: Bin Yang ,  Charles E. Wyman

Inventor： Bin Yang ,  Charles E. Wyman

IPC: C12P7/06 ,  C12P7/08 ,  C12P7/10 ,  C12P19/14 ,  C12P21/06 ,  C07K14/415 ,  C07K14/765

CPC classification number: C12P7/08 ,  C12P7/10 ,  C12P19/02 ,  Y02E50/16 ,  Y02E50/17

Abstract: Disclosed is a method for converting cellulose in a lignocellulosic biomass. The method provides for a lignin-blocking polypeptide and/or protein treatment of high lignin solids. The treatment enhances cellulase availability in cellulose conversion and allows for the determination of optimized pretreatment conditions. Additionally, ethanol yields from a Simultaneous Saccharification and Fermentation process are improved 5-25% by treatment with a lignin-blocking polypeptide and/or protein.

Abstract translation: 公开了一种在木质纤维素生物质中转化纤维素的方法。 该方法提供高木质素固体的木质素阻断多肽和/或蛋白质处理。 该处理增强了纤维素转化中的纤维素酶可用性，并且允许确定优化的预处理条件。 此外，通过用木质素阻断多肽和/或蛋白质处理，来自同时糖化和发酵过程的乙醇产率提高了5-25％。

公开(公告)号：US20130292767A1

公开(公告)日：2013-11-07

申请号：US13465064

申请日：2012-05-07

Applicant: Bin Yang ,  Xia Li ,  Jun Yuan

Inventor： Bin Yang ,  Xia Li ,  Jun Yuan

IPC: H01L27/12 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/28026 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/47 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular embodiment, a CMOS device includes a silicon substrate, a dielectric insulator material on the silicon substrate, and an extension layer on the dielectric insulator material. The CMOS device further includes a gate in contact with a channel and in contact with an extension region. The CMOS device also includes a source in contact with the extension region and a drain in contact with the extension region. The extension region includes a first region in contact with the source and the gate and includes a second region in contact with the drain and the gate.

Abstract translation: 公开了一种互补金属氧化物半导体（CMOS）器件及其形成方法。 在特定实施例中，CMOS器件包括硅衬底，硅衬底上的介电绝缘体材料以及介电绝缘体材料上的延伸层。 CMOS器件还包括与沟道接触并与延伸区域接触的栅极。 CMOS器件还包括与延伸区域接触的源极和与延伸区域接触的漏极。 延伸区域包括与源极和栅极接触的第一区域，并且包括与漏极和栅极接触的第二区域。

公开(公告)号：US08507369B2

公开(公告)日：2013-08-13

申请号：US13659907

申请日：2012-10-24

Applicant: Xubin Jing ,  Bin Yang ,  Mingsheng Guo

Inventor： Xubin Jing ,  Bin Yang ,  Mingsheng Guo

IPC: H01L21/00

CPC classification number: H01L29/66083 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/413 ,  H01L29/66439 ,  H01L29/775

Abstract: The invention provides a method for producing silicon nanowire devices, including the following steps: growing SiNW on a substrate; depositing an amorphous carbon layer and dielectric anti-reflectivity coating orderly; removing part of dielectric anti-reflectivity coating and amorphous carbon layer above the SiNW through dry etching to expose the SiNW device area; depositing an oxide film on the surface of the above structure; forming a metal pad connected with the SiNW in the SiNW device area; depositing a passivation layer on the surface of the above structure; applying photolithography and etching technology to form contact holes on the metal pad and to remove the passivation layer, the oxide film and the dielectric anti-reflectivity coating above the SiNW outside the device area, stopping on the amorphous carbon layer; removing the amorphous carbon layer above the SiNW outside the device area through ashing process to expose the SiNW.

Abstract translation: 本发明提供一种生产硅纳米线器件的方法，包括以下步骤：在衬底上生长SiNW; 有序沉积无定形碳层和电介质抗反射涂层; 通过干蚀刻去除SiNW上方的介电抗反射涂层和无定形碳层的一部分，以暴露SiNW器件区域; 在上述结构的表面上沉积氧化膜; 在SiNW器件区域中形成与SiNW连接的金属焊盘; 在上述结构的表面上沉积钝化层; 施加光刻和蚀刻技术以在金属焊盘上形成接触孔，并在器件区域外的SiNW上方去除钝化层，氧化物膜和介电抗反射涂层，停止在无定形碳层上; 通过灰化处理去除器件区域外的SiNW以上的无定形碳层，以暴露SiNW。

公开(公告)号：US08482084B2

公开(公告)日：2013-07-09

申请号：US12726789

申请日：2010-03-18

Applicant: Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

Inventor： Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

IPC: H01L29/76 ,  H01L31/00

CPC classification number: H01L29/78654 ,  H01L29/7839

Abstract: A Schottky field effect transistor is provided that includes a substrate having a layer of semiconductor material atop a dielectric layer, wherein the layer of semiconductor material has a thickness of less than 10.0 nm. A gate structure is present on the layer of semiconductor material. Raised source and drain regions comprised of a metal semiconductor alloy are present on the layer of semiconductor material on opposing sides of the gate structure. The raised source and drain regions are Schottky source and drain regions. In one embodiment, a first portion of the Schottky source and drain regions that is adjacent to a channel region of the Schottky field effect transistor contacts the dielectric layer, and a non-reacted semiconductor material is present between a second portion of the Schottky source and drain regions and the dielectric layer.

Abstract translation: 提供一种肖特基场效应晶体管，其包括在电介质层顶上具有半导体材料层的衬底，其中半导体材料层的厚度小于10.0nm。 栅极结构存在于半导体材料层上。 在栅极结构的相对侧的半导体材料层上存在由金属半导体合金构成的凸起的源极和漏极区域。 凸起的源极和漏极区域是肖特基源极和漏极区域。 在一个实施例中，与肖特基场效应晶体管的沟道区相邻的肖特基源极和漏极区的第一部分接触电介质层，并且未反应的半导体材料存在于肖特基源的第二部分和 漏区和电介质层。