公开(公告)号：US20240321706A1

公开(公告)日：2024-09-26

申请号：US18474151

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： William George En ,  Samuel Naffziger ,  Regina T. Schmidt ,  Omar Zia ,  John Wuu

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L23/481 ,  H01L23/49816 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A method for implementing shared metal connectivity between 3D stacked circuit dies can include providing a first circuit die having a first metal stack. The method can additionally include providing a second circuit die having a second metal stack, wherein at least one metal layer of the second metal stack is utilized by both the first circuit die and the second circuit die. The method can also include connecting the second metal stack to the first metal stack of the first circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240320293A1

公开(公告)日：2024-09-26

申请号：US18125454

申请日：2023-03-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nallani Bhaskar ,  Mithun Mohan Kadavil Madana Mohanan

IPC: G06F17/16 ,  G06F9/48

CPC classification number: G06F17/16 ,  G06F9/4881

Abstract: Techniques are described in which an estimated optimal thread quantity for matrix multiplication is determined and implemented based on dimensions of the input matrices being multiplied and one or more kernel parameters that vary based on processor architecture. An efficient factorization of the estimated optimal thread quantity is based on a number of blocks along a first dimension of a first input matrix, and a number of blocks along a dimension n of a second input matrix B, with both numbers being based on the kernel parameters. In certain embodiments, a command processor of a parallel processor determines an estimated optimal thread quantity for performing a matrix multiplication command responsive to receiving the matrix multiplication command, and then schedules that estimated optimal thread quantity of kernel threads to execute the matrix multiplication command in parallel.

公开(公告)号：US20240319911A1

公开(公告)日：2024-09-26

申请号：US18731089

申请日：2024-05-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Vamsee Reddy Kommareddy ,  SeyedMohammad SeyedzadehDelcheh ,  Sergey Blagodurov

IPC: G06F3/06 ,  G06F9/50 ,  G06F12/0802

CPC classification number: G06F3/0655 ,  G06F3/0602 ,  G06F3/065 ,  G06F3/0653 ,  G06F9/5027 ,  G06F12/0802 ,  G06F2212/60

Abstract: One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a cache memory of a computing node in the disaggregated memory system executing one or more tasks of a host application is initiated based on the write accesses to the fabric-attached memory module.

公开(公告)号：US20240319712A1

公开(公告)日：2024-09-26

申请号：US18187848

申请日：2023-03-22

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Jerry Anton Ahrens ,  Grant Evan Ley ,  Anil Harwani ,  Amitabh Mehra ,  Joshua Taylor Knight ,  William Robert Alverson ,  Adam Neil Calder Clark

IPC: G05B19/4155 ,  G01K7/01

CPC classification number: G05B19/4155 ,  G01K7/01 ,  G05B2219/49216

Abstract: Dynamic range aware conversion of sensor readings is described. A system includes one or more sensors to sense conditions of a component and output sensor readings and a system manager. The system manager is configured to convert the sensor readings into condition measurements by converting the sensor readings into the condition measurements using a first transformation while operating in a first conversion mode or converting the sensor readings into the condition measurements using a second transformation while operating in a second conversion mode. The system manager then adjusts operation of the component based on the condition measurements.

公开(公告)号：US12101135B2

公开(公告)日：2024-09-24

申请号：US18243243

申请日：2023-09-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Ramon Mangaser ,  Karthik Gopalakrishnan ,  Andy Huei Chu ,  Pradeep Jayaraman

IPC: H04B3/56 ,  G05F1/46 ,  H04B3/06

CPC classification number: H04B3/56 ,  G05F1/46 ,  H04B3/06

Abstract: An integrated circuit includes a first terminal for receiving a data signal, a second terminal for receiving an external reference voltage, a receiver, and a reference voltage generation circuit. The receiver is powered by a power supply voltage with respect to ground and has a first input coupled to the first terminal, a second input for receiving a shared reference voltage, and an output for providing a data input signal. The reference voltage generation circuit is coupled to the second terminal and receives the power supply voltage. The reference voltage generation circuit is operable to form the shared reference voltage by mixing noise from the power supply voltage and noise from the second terminal.

公开(公告)号：US12100464B2

公开(公告)日：2024-09-24

申请号：US18302510

申请日：2023-04-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Joel Thornton Irby ,  Grady L. Giles

IPC: G11C7/10 ,  G11C29/12 ,  G11C29/44 ,  G11C29/46

CPC classification number: G11C29/4401 ,  G11C7/1012 ,  G11C7/1036 ,  G11C7/106 ,  G11C7/1087 ,  G11C29/1201 ,  G11C29/46 ,  G11C2029/1202

Abstract: An integrated circuit includes a latch array including a plurality of latches logically configured in rows and columns, a plurality of repair latches operatively coupled to the plurality of latches and latch array built in self-test and repair logic (LABISTRL) coupled to the plurality of latches. In some implementations the LABISTRL configures latches in the array as one or more column serial test shift register, detects one or more defective latches of the plurality of latches based on applied test data, and selects at least one repair latch in response to detection of at least one defective latch.

公开(公告)号：US12099866B2

公开(公告)日：2024-09-24

申请号：US17135381

申请日：2020-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Jonathan Alsop ,  Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F9/48 ,  G06F3/06 ,  G06F12/02 ,  G06F12/14

CPC classification number: G06F9/485 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0284 ,  G06F12/0292 ,  G06F12/145

Abstract: An Address Mapping-Aware Tasking (AMAT) mechanism manages compute task data and issues compute tasks on behalf of threads that created the compute task data. The AMAT mechanism stores compute task data generated by host threads in a set of partitions, where each partition is designated for a particular memory module. The AMAT mechanism maintains address mapping data that maps address information to partitions. Threads push compute task data to the AMAT mechanism instead of generating and issuing their own compute tasks. The AMAT mechanism uses address information included in the compute task data and the address mapping data to determine partitions in which to store the compute task data. The AMAT mechanism then issues compute tasks to be executed near the corresponding memory modules (i.e., in PIM execution units or NUMA compute nodes) based upon the compute task data stored in the partitions.

公开(公告)号：US12099789B2

公开(公告)日：2024-09-24

申请号：US17118442

申请日：2020-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin Y. Cheng ,  Sooraj Puthoor ,  Onur Kayiran

IPC: G06F30/331 ,  G06F9/38 ,  G06F30/34

CPC classification number: G06F30/331 ,  G06F9/3877 ,  G06F30/34

Abstract: Methods, devices, and systems for information communication. Information transmitted from a host to a graphics processing unit (GPU) is received by information analysis circuitry of a field-programmable gate array (FPGA). A pattern in the information is determined by the information analysis circuitry. A predicted information pattern is determined, by the information analysis circuitry, based on the information. An indication of the predicted information pattern is transmitted to the host. Responsive to a signal from the host based on the predicted information pattern, the FPGA is reprogrammed to implement decompression circuitry based on the predicted information pattern. In some implementations, the information includes a plurality of packets. In some implementations, the predicted information pattern includes a pattern in a plurality of packets. In some implementations, the predicted information pattern includes a zero data pattern.

公开(公告)号：US12099723B2

公开(公告)日：2024-09-24

申请号：US17956614

申请日：2022-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  Marko Scrbak

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: A method for operating a memory having a plurality of banks accessible in parallel, each bank including a plurality of grains accessible in parallel is provided. The method includes: based on a memory access request that specifies a memory address, identifying a set that stores data for the memory access request, wherein the set is spread across multiple grains of the plurality of grains; and performing operations to satisfy the memory access request, using entries of the set stored across the multiple grains of the plurality of grains.

公开(公告)号：US12099451B2

公开(公告)日：2024-09-24

申请号：US17489726

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/12 ,  G06F12/122 ,  G06F12/123 ,  G06F12/127

CPC classification number: G06F12/122 ,  G06F12/123 ,  G06F12/124 ,  G06F12/127 ,  G06F2212/60

Abstract: Systems and methods for cache replacement are disclosed. Techniques are described that determine a re-reference interval prediction (RRIP) value of respective data blocks in a cache, where an RRIP value represents a likelihood that a respective data block will be re-used within a time interval. Upon an access, by a processor, to a data segment in a memory, if the data segment is not stored in the cache, a data block in the cache to be replaced by the data segment is selected, utilizing a binary tree that tracks recency of data blocks in the cache.