公开(公告)号：US20240290846A1

公开(公告)日：2024-08-29

申请号：US18572595

申请日：2022-04-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Qun LIU ,  Song ZHANG ,  Yaohui ZHOU ,  Dejin WANG ,  Wenming ZHU

IPC: H01L29/40 ,  H01L29/45

CPC classification number: H01L29/401 ,  H01L29/456

Abstract: A forming method for a floating contact hole, and a semiconductor device. The method comprises: obtaining a substrate, and forming a tunnel oxide layer and a plurality of gates on the substrate; forming a metal silicide barrier layer; forming a self-aligned metal silicide; forming an interlayer dielectric layer; performing photoetching on the interlayer dielectric layer to obtain a photoresist pattern, the photoresist pattern comprising a small adhesive strip in the middle of the floating contact hole; and etching the floating contact hole by using the photoresist pattern as an etching mask layer.

公开(公告)号：US20240234520A9

公开(公告)日：2024-07-11

申请号：US18277658

申请日：2021-07-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： CHUNXU LI ,  FENG LIN ,  SHUXIAN CHEN ,  HONGFENG JIN ,  HUAJUN JIN ,  GANG HUANG ,  YU HUANG ,  BIN YANG

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/66681 ,  H01L29/7816

Abstract: A laterally diffused metal oxide semiconductor device and a preparation method thereof are disclosed. The semiconductor device includes: a substrate; a body region having a first conductivity type and formed in the substrate; a drift region, having a second conductivity type, formed in the substrate and adjacent to the body region; a field plate structure, formed on the drift region, a lower surface of an end of the field plate structure close to the body region being flush with the upper surface of the substrate, and the end of the field plate structure close to the body region also having an upwardly extending inclined surface; and a drain region, having a second conductivity type, formed in an upper layer of the drift region, and in contact with the end of the field plate structure away from the body region.

公开(公告)号：US12022270B2

公开(公告)日：2024-06-25

申请号：US17761669

申请日：2020-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jiale Su ,  Guoping Zhou ,  Xinwei Zhang ,  Changfeng Xia

IPC: H04R19/04 ,  B81C1/00 ,  H04R31/00

CPC classification number: H04R31/003 ,  B81C1/00158 ,  H04R19/04 ,  B81C2201/0105 ,  B81C2201/0116 ,  B81C2201/0133 ,  H04R2201/003

Abstract: A preparation method for a micro-electromechanical systems (MEMS) microphone includes the steps of: providing a silicon substrate having a silicon surface; forming an enclosed cavity in the silicon substrate; forming a plurality of spaced apart acoustic holes in the silicon substrate, each acoustic hole having two openings, one of which communicating with the cavity and the other one located on the silicon surface; forming a sacrificial layer on the silicon substrate, which includes a first filling portion, a second filling portion and a shielding portion; forming a polysilicon layer on the shielding portion; forming a recess in the silicon substrate on the side away from the silicon surface; and removing the first filling portion, the second filling portion and part of the shielding portion so that the recess is brought into communication with the cavity to form a back chamber, and that the polysilicon layer, the remainder of the shielding portion and the silicon substrate together delimit a hollow chamber, the hollow chamber communicating with the opening of the plurality of acoustic holes away from the cavity, completing the MEMS microphone.

公开(公告)号：US11887979B2

公开(公告)日：2024-01-30

申请号：US17267835

申请日：2019-08-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/866

CPC classification number: H01L27/0255 ,  H01L27/0262 ,  H01L27/0296 ,  H01L29/66106 ,  H01L29/866

Abstract: A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.

公开(公告)号：US20240006492A1

公开(公告)日：2024-01-04

申请号：US18258180

申请日：2021-08-10

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Dong FANG ,  Kui XIAO

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/1095 ,  H01L29/41741 ,  H01L29/7813 ,  H01L21/26513 ,  H01L29/66727 ,  H01L29/66734

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method therefor. The semiconductor device includes: a base, where a first surface of the base is provided with a first trench and a second trench; a gate, provided in the first trench; a gate insulation isolation structure, provided in the first trench, wherein the gate insulation isolation structure covers the gate at a bottom, sides and a top of the gate; a source doped region, provided in the base, on both sides of the first trench and on both sides of the second trench; a trench conductive structure, provided in the second trench; a source electrode, provided on the trench conductive structure and the source doped region, and electrically connected to the trench conductive structure and the source doped region; and a drain electrode, provided on a second surface of the base. The semiconductor device in the present disclosure, in addition to be conducted through a channel, can also be conducted through the trench conductive structure; thus, conductivity thereof is stronger. Since the channel conducts faster, a turn-on voltage (forward voltage drop) thereof is lower.

公开(公告)号：US20240006477A1

公开(公告)日：2024-01-04

申请号：US18254986

申请日：2022-07-22

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yongshun LI ,  Huajun JIN ,  Liang SONG

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36

CPC classification number: H01L29/0634 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/36

Abstract: A manufacturing method for a super-β bipolar junction transistor includes providing a substrate, and forming a first conductive type isolation buried layer and a first conductive type doped layer based on the substrate. The isolation buried layer is located at a bottom of the doped layer. The method also includes forming a second conductive type base region in the doped layer and forming a second conductive type doped island on a peripheral side of the base region. A doping concentration of the doped island is greater than that of the base region. Additionally, the method includes forming a first conductive type collector region in the doped layer, and the collector region is spaced from the base region. Further, the method includes forming a first conductive type emitter region in the base region.

公开(公告)号：US11777416B2

公开(公告)日：2023-10-03

申请号：US17418606

申请日：2019-12-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Weifeng Sun ,  Huaxin Zhang ,  Hu Zhang ,  Menglin Yu ,  Siyu Zhao ,  Shen Xu ,  Longxing Shi

IPC: H02M3/335

CPC classification number: H02M3/33592

Abstract: A flyback converter and an output voltage acquisition method therefor and apparatus thereof, wherein the output voltage acquisition method comprises the following steps: acquiring the reference output voltage of a flyback converter; sampling the current output voltage of the flyback converter within a reset time of each switching period among M continuous switching periods of the flyback converter, wherein M is a positive integer; and according to the reference output voltage and the current output voltage, sampling a dichotomy to successively approximate the current output voltage until the M switching periods are finished, and acquiring the output voltage of the flyback converter.

公开(公告)号：US20230154549A1

公开(公告)日：2023-05-18

申请号：US17916927

申请日：2021-04-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Bin CHEN ,  Youhui LI ,  Ming GU ,  Xinmiao ZHAO ,  Hao WANG ,  Shuming GUO ,  Zongchuan WANG ,  Nan ZHANG

IPC: G11C16/30 ,  G11C16/26

CPC classification number: G11C16/30 ,  G11C16/26

Abstract: A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is “0”; and clamping the output end at a clamping voltage when the first signal is “1”.

公开(公告)号：US11605641B2

公开(公告)日：2023-03-14

申请号：US17257087

申请日：2019-10-12

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Song Zhang ,  Zhibin Liang ,  Yan Jin ,  Dejin Wang

IPC: H01L27/11521

Abstract: A flash device and a manufacturing method thereof. The method comprises: providing a substrate, and forming, on the substrate, a floating gate polycrystalline layer, a floating gate oxide layer, and a tunneling oxide layer; wherein the floating gate polycrystalline layer is formed on the substrate, the floating gate oxide layer is formed between the substrate and the floating gate polycrystalline layer, a substrate region at one side of the floating gate polycrystalline layer is a first substrate region, a substrate region at the other side of the floating gate polycrystalline layer is a second substrate region; forming, on the tunneling oxide layer, located in the first substrate region, a continuous non-conductive layer, the non-conductive layer extending to the tunneling oxide layer at a side wall of the floating gate polycrystalline layer; and forming, on the tunneling oxide layer, a polysilicon layer.

公开(公告)号：US20230067583A1

公开(公告)日：2023-03-02

申请号：US17796952

申请日：2021-05-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chen LI ,  Hao WANG

IPC: G01J5/12

Abstract: An analog-to-digital converter and a thermopile array. The analog-to-digital converter comprises: a reference voltage generation circuit comprising a voltage generation unit; a chopping modulation unit used to perform chopping modulation on a voltage signal generated by the voltage generation unit, and to modulate low frequency noise of the voltage signal into high frequency noise; and a low-pass filter used to eliminate the high frequency noise to obtain a reference voltage. The invention employs a simple structure to obtain a low noise reference voltage at low costs.