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公开(公告)号：US11777416B2
公开(公告)日：2023-10-03
申请号：US17418606
申请日：2019-12-19
发明人： Weifeng Sun , Huaxin Zhang , Hu Zhang , Menglin Yu , Siyu Zhao , Shen Xu , Longxing Shi
IPC分类号： H02M3/335
CPC分类号： H02M3/33592
摘要： A flyback converter and an output voltage acquisition method therefor and apparatus thereof, wherein the output voltage acquisition method comprises the following steps: acquiring the reference output voltage of a flyback converter; sampling the current output voltage of the flyback converter within a reset time of each switching period among M continuous switching periods of the flyback converter, wherein M is a positive integer; and according to the reference output voltage and the current output voltage, sampling a dichotomy to successively approximate the current output voltage until the M switching periods are finished, and acquiring the output voltage of the flyback converter.
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公开(公告)号：US20230154549A1
公开(公告)日：2023-05-18
申请号：US17916927
申请日：2021-04-28
发明人： Bin CHEN , Youhui LI , Ming GU , Xinmiao ZHAO , Hao WANG , Shuming GUO , Zongchuan WANG , Nan ZHANG
摘要： A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is “0”; and clamping the output end at a clamping voltage when the first signal is “1”.
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公开(公告)号：US11605641B2
公开(公告)日：2023-03-14
申请号：US17257087
申请日：2019-10-12
发明人： Song Zhang , Zhibin Liang , Yan Jin , Dejin Wang
IPC分类号： H01L27/11521
摘要： A flash device and a manufacturing method thereof. The method comprises: providing a substrate, and forming, on the substrate, a floating gate polycrystalline layer, a floating gate oxide layer, and a tunneling oxide layer; wherein the floating gate polycrystalline layer is formed on the substrate, the floating gate oxide layer is formed between the substrate and the floating gate polycrystalline layer, a substrate region at one side of the floating gate polycrystalline layer is a first substrate region, a substrate region at the other side of the floating gate polycrystalline layer is a second substrate region; forming, on the tunneling oxide layer, located in the first substrate region, a continuous non-conductive layer, the non-conductive layer extending to the tunneling oxide layer at a side wall of the floating gate polycrystalline layer; and forming, on the tunneling oxide layer, a polysilicon layer.
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公开(公告)号：US20230067583A1
公开(公告)日：2023-03-02
申请号：US17796952
申请日：2021-05-27
IPC分类号： G01J5/12
摘要： An analog-to-digital converter and a thermopile array. The analog-to-digital converter comprises: a reference voltage generation circuit comprising a voltage generation unit; a chopping modulation unit used to perform chopping modulation on a voltage signal generated by the voltage generation unit, and to modulate low frequency noise of the voltage signal into high frequency noise; and a low-pass filter used to eliminate the high frequency noise to obtain a reference voltage. The invention employs a simple structure to obtain a low noise reference voltage at low costs.
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公开(公告)号：US11557959B2
公开(公告)日：2023-01-17
申请号：US16959015
申请日：2018-12-29
发明人： Shen Xu , Minggang Chen , Hao Wang , Jinyu Xiao , Wei Su , Weifeng Sun , Longxing Shi
摘要： An automatic dead zone time optimization system in a primary-side regulation flyback power supply continuous conduction mode (CCM), including a closed loop formed by a control system, including a single output digital to analog converter (DAC) midpoint sampling module, a digital control module, a current detection module, a dead zone time calculation module and a pulse-width modulation (PWM) driving module, and a controlled synchronous rectification primary-side regulation flyback converter. A primary-side current is sampled using a DAC Sampling mechanism to calculate a secondary-side average current, so as to obtain a primary-side average current and a secondary-side average current, in the case of CCM. A secondary-side current is input into the dead zone time calculation module to obtain a reasonable dead zone time; and the PWM driving module is jointly controlled by a primary-side regulation loop and the obtained dead zone time.
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公开(公告)号：US11552164B2
公开(公告)日：2023-01-10
申请号：US17265565
申请日：2019-08-09
发明人： Huajun Jin , Guipeng Sun
IPC分类号： H01L21/22 , H01L21/26 , H01L29/06 , H01L21/225 , H01L21/265 , H01L21/266 , H01L29/10 , H01L29/66 , H01L29/78
摘要： A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.
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公开(公告)号：US20220386052A1
公开(公告)日：2022-12-01
申请号：US17761669
申请日：2020-05-26
发明人： Jiale SU , Guoping ZHOU , Xinwei ZHANG , Changfeng XIA
摘要： A preparation method for a micro-electromechanical systems (MEMS) microphone includes the steps of: providing a silicon substrate having a silicon surface; forming an enclosed cavity in the silicon substrate; forming a plurality of spaced apart acoustic holes in the silicon substrate, each acoustic hole having two openings, one of which communicating with the cavity and the other one located on the silicon surface; forming a sacrificial layer on the silicon substrate, which includes a first filling portion, a second filling portion and a shielding portion; forming a polysilicon layer on the shielding portion; forming a recess in the silicon substrate on the side away from the silicon surface; and removing the first filling portion, the second filling portion and part of the shielding portion so that the recess is brought into communication with the cavity to form a back chamber, and that the polysilicon layer, the remainder of the shielding portion and the silicon substrate together delimit a hollow chamber, the hollow chamber communicating with the opening of the plurality of acoustic holes away from the cavity, completing the MEMS microphone.
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公开(公告)号：US11387349B2
公开(公告)日：2022-07-12
申请号：US17265587
申请日：2019-10-14
发明人： Yan Gu , Shikang Cheng , Sen Zhang
摘要： A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.
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89.发明授权公开(公告)号：US11336217B2
公开(公告)日：2022-05-17
申请号：US16958868
申请日：2018-12-29
发明人： Rui Zhong , Mingshu Zhang , Sen Zhang , Jinyu Xiao , Wei Su , Weifeng Sun , Longxing Shi
摘要： A method and an apparatus for reducing noise of a switched reluctance motor, includes: supplying a PWM signal as a driving signal to a driving circuit of a switched reluctance motor; and varying a carrier frequency of the PWM signal as an operation period of the switched reluctance motor varies; if the switched reluctance motor changes phase, determining that the operation period of the switched reluctance motor varies.
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公开(公告)号：US20220115532A1
公开(公告)日：2022-04-14
申请号：US17417677
申请日：2019-12-23
发明人： Weifeng SUN , Rongcheng LOU , Kui XIAO , Feng LIN , Jiaxing WEI , Sheng LI , Siyang LIU , Shengli LU , Longxing SHI
摘要： A power semiconductor device includes a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.
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