公开(公告)号：US09408574B2

公开(公告)日：2016-08-09

申请号：US13867166

申请日：2013-04-22

申请人： Medtronic, Inc.

发明人： Robert W. Stadler ,  Li Wang

IPC分类号： A61B5/053 ,  A61B5/00 ,  A61N1/05 ,  A61N1/362 ,  G06F12/08

CPC分类号： A61B5/0538 ,  A61B5/0537 ,  A61B5/4875 ,  A61B5/686 ,  A61B5/7275 ,  A61N1/362 ,  A61N1/3627 ,  A61N1/36521 ,  G06F12/0862 ,  G06F12/0877

摘要： A method and apparatus for detection of changes in impedance a patient that includes generating measured impedances, generating an adaptive baseline trend of the measured impedances corresponding to a first time period, generating a short term trend of the measured impedances corresponding to a second time period less than the first time period, determining changes in relative position of the short term trend and the baseline trend, the determined changes in relative position corresponding to determining intersecting of the baseline trend by the short term trend, determining differences between the baseline trend and calculated period average impedances, and accumulating, in response to determining no intersecting of the baseline trend by the short term trend, the determined differences between the baseline trend and the calculated period average impedances.

公开(公告)号：US20160210238A1

公开(公告)日：2016-07-21

申请号：US15001652

申请日：2016-01-20

申请人： ULTRATA LLC

发明人： Steven Frank ,  Larry Reback

IPC分类号： G06F12/08 ,  G06F3/06

CPC分类号： G06F3/0604 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0635 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0683 ,  G06F3/0685 ,  G06F12/0817 ,  G06F12/0837 ,  G06F12/0877 ,  G06F2212/2542 ,  G06F2212/6012

摘要： Embodiments of the invention provide systems and methods to implement an object memory fabric. Object memory modules may include object storage storing memory objects, memory object meta-data, and a memory module object directory. Each memory object and/or memory object portion may be created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects and/or portions within the object memory module. A hierarchy of object routers may communicatively couple the object memory modules. Each object router may maintain an object cache state for the memory objects and/or portions contained in object memory modules below the object router in the hierarchy. The hierarchy, based on the object cache state, may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the object cache state.

摘要翻译： 本发明的实施例提供了实现对象存储器结构的系统和方法。 对象存储器模块可以包括存储存储器对象，存储器对象元数据和存储器模块对象目录的对象存储。 可以在对象存储器模块内本地创建每个存储器对象和/或存储器对象部分，并且可以在存储器层处被管理。 存储器模块对象目录可以对对象存储器模块内的所有存储器对象和/或部分进行索引。 对等路由器的层次结构可以通信地耦合目标存储器模块。 每个对象路由器可以为层次结构中的对象路由器下方的存储器对象和/或包含在对象存储器模块中的部分保持对象缓存状态。 基于对象高速缓存状态的层次结构可以作为通信地耦合到所有对象存储器模块并且基于对象高速缓存状态来处理请求的单个对象目录进行聚合。

公开(公告)号：US20160210053A1

公开(公告)日：2016-07-21

申请号：US15001451

申请日：2016-01-20

申请人： ULTRATA LLC

发明人： STEVEN FRANK ,  LARRY REBACK

IPC分类号： G06F3/06 ,  H04L29/08

CPC分类号： G06F3/0604 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0635 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0683 ,  G06F3/0685 ,  G06F12/0817 ,  G06F12/0837 ,  G06F12/0877 ,  G06F2212/2542 ,  G06F2212/6012

摘要： Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments can implement an object memory fabric including object memory modules storing memory objects created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects within the object memory module. A hierarchy of object routers communicatively coupling the object memory modules may each include a router object directory that indexes all memory objects and portions contained in object memory modules below the object router in the hierarchy. The hierarchy of object routers may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the router object directories.

摘要翻译： 本发明的实施例提供了用于管理处理，存储器，存储，网络和云计算的系统和方法，以显着提高处理节点的效率和性能。 实施例可以实现包括对象存储器模块的对象存储器结构，该对象存储器模块存储在对象存储器模块内本地创建的存储器对象，并且可以在存储器层进行管理。 内存模块对象目录可能会索引对象内存模块中的所有内存对象。 通信地耦合对象存储器模块的对等路由器的层次结构可以各自包括路由器对象目录，其对层级中的对象路由器下面的对象存储器模块中的所有存储器对象和包含的对象存储器模块中 对等路由器的层次结构可以作为单个对象目录进行聚合，通信地耦合到所有对象存储器模块并且基于路由器对象目录来处理请求。

公开(公告)号：US20160196214A1

公开(公告)日：2016-07-07

申请号：US14890902

申请日：2014-12-14

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： RODNEY E. HOOKER ,  DOUGLAS R. REED ,  JOHN MICHAEL GREER ,  COLIN EDDY ,  ALBERT J. LOPER

IPC分类号： G06F12/08

CPC分类号： G06F12/0877 ,  G06F12/0864 ,  G06F12/0893 ,  G06F12/122 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/1021 ,  G06F2212/502 ,  G06F2212/604

摘要： A fully associative cache memory, comprising: an array of storage elements; an allocation unit that allocates the storage elements in response to memory accesses that miss in the cache memory. Each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. Each valid storage element of the array has an associated MAT. For each MAT, the allocation unit maintains: a counter that counts of a number of valid storage elements associated with the MAT; and a corresponding threshold. The allocation unit allocates into any of the storage elements in response to a memory access that misses in the cache, unless the counter of the MAT of the memory access has reached the corresponding threshold, in which case the allocation unit replaces one of the valid storage elements associated with the MAT of the memory access.

摘要翻译： 一种完全关联的高速缓冲存储器，包括：一组存储元件; 分配单元，其响应于在高速缓冲存储器中缺失的存储器访问来分配存储元件。 每个存储器访问具有多个预定MAT的相关联的存储器访问类型（MAT）。 数组的每个有效存储元素都有一个关联的MAT。 对于每个MAT，分配单元维护：计数与MAT相关联的多个有效存储元素的计数器; 和相应的阈值。 除非存储器访问的MAT的计数器已达到相应的阈值，否则分配单元响应于高速缓存中缺少的存储器访问而分配到任何存储元件中，在这种情况下，分配单元替换有效存储器 与MAT相关的元素的内存访问。

公开(公告)号：US09348756B2

公开(公告)日：2016-05-24

申请号：US14523153

申请日：2014-10-24

申请人： IP Cube Partners (ICP) Co., Ltd.

发明人： Moon J. Kim

IPC分类号： G06F12/08

CPC分类号： G06F12/0884 ,  G06F12/0806 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0835 ,  G06F12/0877 ,  G06F2212/6012 ,  G06F2212/62 ,  G06F2212/621

摘要： In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.

公开(公告)号：US09323672B2

公开(公告)日：2016-04-26

申请号：US14585573

申请日：2014-12-30

申请人： Intel Corporation

发明人： Daehyun Kim ,  Christopher J. Hughes ,  Yen-Kuang Chen ,  Partha Kundu

IPC分类号： G06F12/08 ,  G11C7/10

CPC分类号： G06F12/0806 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/6026 ,  G06F2212/62 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/13

摘要： A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

公开(公告)号：US09317437B2

公开(公告)日：2016-04-19

申请号：US14726820

申请日：2015-06-01

申请人： IP Cube Partners (ICP) Co., Ltd.

发明人： Moon J. Kim

IPC分类号： G06F12/08

CPC分类号： G06F12/0884 ,  G06F12/0806 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0835 ,  G06F12/0877 ,  G06F2212/6012 ,  G06F2212/62 ,  G06F2212/621

摘要： In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.

公开(公告)号：US09313271B2

公开(公告)日：2016-04-12

申请号：US14704059

申请日：2015-05-05

申请人： NETAPP, INC.

发明人： Narayan Venkat ,  David Lively ,  Kenny Speer

IPC分类号： G06F12/00 ,  H04L29/08 ,  G06F3/06

CPC分类号： H04L67/1095 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0683 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0866 ,  G06F12/0877 ,  H04L67/1097

摘要： Described herein is a system and method for maintaining cache coherency. The system and method may maintain coherency for a cache memory that is coupled to a plurality of primary storage devices. The system and method may write data to the cache memory and associate the data with a cache generation identification (ID). A different cache generation ID may be associated with each new set of data that is written to the cache memory. The cache generation ID may be written to the primary storage devices. A backup restore operation may be performed on one of the primary storage devices and a backup restore notification may be received. In response to the notification, the system and method may compare the cache generation ID with the generation ID stored on the restored primary storage device and invalidate data stored on the cache memory for the restored primary storage device.

公开(公告)号：US09286227B2

公开(公告)日：2016-03-15

申请号：US14694315

申请日：2015-04-23

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kevin J. Ash ,  Michael T. Benhase ,  Lokesh M. Gupta ,  David B. Whitworth

IPC分类号： G06F13/28 ,  G06F12/08 ,  G06F13/40 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F12/0871 ,  G06F12/0804 ,  G06F12/0855 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0877 ,  G06F13/4068 ,  G06F13/4221 ,  G06F2212/462 ,  G06F2212/603 ,  G06F2212/604

摘要： For a plurality of input/output (I/O) operations waiting to assemble complete data tracks from data segments, a process, separate from a process responsible for the data assembly into the complete data tracks is initiated, and the at least one complete data track is removed off of a free list by a first I/O waiter.

摘要翻译： 对于等待从数据段组装完整的数据轨迹的多个输入/输出（I / O）操作，启动与负责数据组合到整个数据轨道的过程分离的过程，并且至少一个完整数据 第一个I / O服务员将轨道从免费列表中删除。

公开(公告)号：US20150339230A1

公开(公告)日：2015-11-26

申请号：US14816998

申请日：2015-08-03

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Robert M. Dinkjian ,  Robert S. Horton ,  Michael Y. Lee ,  Bill N. On

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0831 ,  G06F3/0653 ,  G06F12/00 ,  G06F12/0815 ,  G06F12/0877 ,  G06F12/128 ,  G06F13/1631 ,  G06F2212/603 ,  G06F2212/621

摘要： Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.