利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

968 records (took 0.026 seconds)

    Edge synchronized phase-locked loop circuit
    81.
    发明授权
    Edge synchronized phase-locked loop circuit 有权
    边沿同步锁相环电路

    公开(公告)号：US06891441B2

    公开(公告)日：2005-05-10

    申请号：US10295684

    申请日：2002-11-15

    Applicant: Gregor Benedikt Rochow

    Inventor： Gregor Benedikt Rochow

    IPC: H03L7/081 ,  H03L7/183 ,  H03L7/00

    CPC classification number: H03L7/081 ,  H03L7/183

    Abstract: A phase-locked loop circuit for synchronizing an edge of an output signal with an edge of an input signal. The circuit detects an edge of an input clock signal, and a corresponding edge on an output signal. If the output signal edge is out of phase with the input clock edge, the circuit shifts the output signal by 180 degrees to effectively produce a single double-length clock phase. The synchronized phase-locked loop circuit provides predictable phase-locked loop output phase synchronization with an input clock.

    Abstract translation: 一种用于使输出信号的边沿与输入信号的边沿同步的锁相环电路。 电路检测输入时钟信号的边沿和输出信号上的相应边沿。 如果输出信号边沿与输入时钟边沿不同相，则电路将输出信号移位180度，以有效地产生单个双长度时钟相位。 同步锁相环电路提供与输入时钟的可预测的锁相环输出相位同步。

    Use of configurable capacitors to tune a self biased phase locked loop
    83.
    发明授权
    Use of configurable capacitors to tune a self biased phase locked loop 有权
    使用可配置电容调谐自偏置锁相环

    公开(公告)号：US06873214B2

    公开(公告)日：2005-03-29

    申请号：US10138391

    申请日：2002-05-03

    Applicant: Michael Harwood

    Inventor： Michael Harwood

    IPC: H03L7/089 ,  H03L7/093 ,  H03L7/183 ,  H03L7/60

    CPC classification number: H03L7/093 ,  H03L7/0893 ,  H03L7/183 ,  H03L2207/04 ,  H03L2207/06

    Abstract: A phase locked loop (PLL) comprising an input, an output, a charge generator, a low pass filter 3, an oscillator 4 and a frequency divider 5. The frequency divider 5 has an input coupled to the output of the PLL and an output coupled to an input of the charge generator. The frequency at the output of the frequency divider 5 is equal to the frequency at the input of the frequency divider divided by a selectable divider ratio N. The PLL has a damping factor z and a bandwidth to compare frequency ratio ω3/ωref. The low pass filter 3 has a first capacitor for integrating the charge produced by the charge generator. The capacitance of that first capacitor is arranged to be proportional to the divider ratio N so that the damping factor z and the bandwidth to compare frequency ratio ω3/ωref are substantially independent of the divider ratio N.

    Abstract translation: 包括输入，输出，电荷发生器，低通滤波器3，振荡器4和分频器5的锁相环（PLL）。分频器5具有耦合到PLL的输出的输入和输出 耦合到电荷发生器的输入。 分频器5的输出端的频率等于分频器输入端的频率除以可选择的分频比N. PLL具有阻尼系数z和带宽以比较频率比ω3/ωgaref。 低通滤波器3具有用于对由电荷发生器产生的电荷进行积分的第一电容器。 该第一电容器的电容被布置成与分频比N成比例，使得阻尼因子z和比较频率比ω3/ωgaref的带宽基本上与分频比N无关。

    Double-data rate phase-locked-loop with phase aligners to reduce clock skew
    84.
    发明授权
    Double-data rate phase-locked-loop with phase aligners to reduce clock skew 失效
    具有相位对准器的双数据速率锁相环，以减少时钟偏移

    公开(公告)号：US06859109B1

    公开(公告)日：2005-02-22

    申请号：US10250000

    申请日：2003-05-27

    Applicant: Gerry C. T. Leung ,  Howard C. Luong

    Inventor： Gerry C. T. Leung ,  Howard C. Luong

    IPC: H03B5/12 ,  H03L7/099 ,  H03L7/183 ,  H03B27/00

    CPC classification number: H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B2200/0078 ,  H03L7/183

    Abstract: A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for the PLL output. Phases between the PLL's input and output are inherently aligned. The analog output of the analog divider is converted to a digital clock signal and applied to a cascade of digital dividers to generate a reduced feedback clock. The reduced feedback clock is applied to the D input and the digital clock signal is applied to the clock input of a pseudo D-flip-flop that drives the feedback input of a phase-frequency detector that drives the charge pump to the VCO input. Another cascade of digital dividers and pseudo D-flip-flop re-align the reference clock input to the phase-frequency detector. Analog and digital re-alignment circuits reduce internal skew.

    Abstract translation: 锁相环（PLL）在反馈路径中具有模拟分频器，其接收来自压控振荡器（VCO）的同相或正交相输出对，而另一对，90度外 VCO的输出相位用于PLL输出。 PLL的输入和输出之间的相位固有地对齐。 模拟分频器的模拟输出转换为数字时钟信号，并应用于级联的数字分频器以产生减小的反馈时钟。 减小的反馈时钟被施加到D输入，并且数字时钟信号被施加到伪D触发器的时钟输入，该伪D触发器驱动将电荷泵驱动到VCO输入的相位频率检测器的反馈输入。 数字分频器和伪D触发器的另一个级联将参考时钟输入重新对准相位频率检测器。 模拟和数字重新对准电路减少内部偏移。

    Information recording and reproducing apparatus
    85.
    发明申请
    Information recording and reproducing apparatus 失效
    信息记录和再现装置

    公开(公告)号：US20040240349A1

    公开(公告)日：2004-12-02

    申请号：US10851219

    申请日：2004-05-24

    Inventor： Yoshitaka Shimoda ,  Akira Shimizu ,  Yuji Tawaragi

    IPC: G11B007/00 ,  G11B005/09

    CPC classification number: G11B27/24 ,  G11B20/1403 ,  G11B2220/216 ,  G11B2220/218 ,  G11B2220/2562 ,  H03L7/081 ,  H03L7/183

    Abstract: An information recording and reproducing apparatus performs information recording and reproducing on an optical disc having a recording track wobbled by a predetermined frequency, such as a DVD-RW. The information recording and reproducing apparatus includes an optical pickup which irradiates a laser light on the optical disc and receives the laser light reflected by the optical disc to output an electric signal corresponding to the laser light, a push-pull signal generating unit which includes a sample-hold unit and generates the sample-hold push-pull signal and the non-sample-hold push-pull signal from the electric signal, a sample-hold circuit which samples and holds the push-pull signal, a recording clock generating unit which generates a recording clock synchronized with the wobble signal based on the sample-hold push-pull signal during recording and based on the non-sample-hold push-pull signal during reproduction, and a phase adjusting unit which adjusts the phases of the non-sample-hold push-pull signal and the sample-hold push-pull signal. Since the phase delay given to the push-pull signal is corrected by the sample-hold process, the phase difference of the recording clock during recording and reproducing is removed, and it is always possible to perform information recording with high accuracy based on the stable recording clock.

    Abstract translation: 信息记录和再现装置在具有以预定频率摆动的记录磁道的光盘（例如DVD-RW）上执行信息记录和再现。 信息记录和再现装置包括：光学拾取器，其将激光照射在光盘上并接收由光盘反射的激光以输出与激光对应的电信号;推挽信号产生单元，包括： 采样保持单元，从电信号产生采样保持推挽信号和非采样保持推挽信号，采样保持推挽信号的采样保持电路，记录时钟产生单元 其根据记录期间的采样保持推挽信号和再现期间的非采样保持推挽信号产生与摆动信号同步的记录时钟;以及相位调整单元，其调整非采样保持推挽信号的相位， 采样保持推挽信号和采样保持推挽信号。 由于通过采样保持处理来校正给予推挽信号的相位延迟，所以在记录和再现期间记录时钟的相位差被去除，并且总是可以基于稳定的高精度执行高精度的信息记录 录音时钟。

    Low noise divider module for use in a phase locked loop and other applications
    86.
    发明申请
    Low noise divider module for use in a phase locked loop and other applications 失效
    低噪声分频器模块，用于锁相环和其他应用

    公开(公告)号：US20040196940A1

    公开(公告)日：2004-10-07

    申请号：US10406178

    申请日：2003-04-03

    Inventor： Hung-Ming (Ed) Chien

    IPC: H03D003/24

    CPC classification number: H03K23/665 ,  H03K21/10 ,  H03L7/183

    Abstract: A low noise divider module includes a divider chain and a retiming module. The divider chain includes a plurality of cascaded dividers and a plurality of load logic gates. The plurality of cascaded dividers are operably coupled to divide an input oscillation by a divider value, which is programmable, to produce a divided output oscillation based on the load signals provided by the logic gates. The retiming module includes a duty cycle module and a jitter reduction module. The duty cycle module is coupled to produce a duty cycle controlled output oscillation based on a representation of the divided output oscillation produced by the divider chain in accordance with a duty cycle setting signal. The jitter reduction module is operably coupled to produce a low jitter output oscillation from the duty cycle controlled output oscillation based on the input oscillation and the duty cycle setting signal.

    Abstract translation: 低噪声分频器模块包括分频器链和重定时模块。 分压器链包括多个级联分压器和多个负载逻辑门。 多个级联分压器可操作地耦合以将输入振荡除以可编程的分频器值，以基于由逻辑门提供的负载信号产生分频输出振荡。 重定时模块包括占空比模块和抖动减少模块。 占空比模块被耦合以根据占空比设置信号基于由分频器链产生的分频输出振荡的表示来产生占空比控制的输出振荡。 抖动降低模块可操作地耦合以基于输入振荡和占空比设置信号从占空比控制的输出振荡产生低抖动输出振荡。

    Edge synchronized phase-locked loop circuit
    87.
    发明申请
    Edge synchronized phase-locked loop circuit 有权
    边沿同步锁相环电路

    公开(公告)号：US20040095189A1

    公开(公告)日：2004-05-20

    申请号：US10295684

    申请日：2002-11-15

    Inventor： Gregor Benedikt Rochow

    IPC: H03L007/00

    CPC classification number: H03L7/081 ,  H03L7/183

    Abstract: A phase-locked loop circuit for synchronizing an edge of an output signal with an edge of an input signal. The circuit detects an edge of an input clock signal, and a corresponding edge on an output signal. If the output signal edge is out of phase with the input clock edge, the circuit shifts the output signal by 180 degrees to effectively produce a single double-length clock phase. The synchronized phase-locked loop circuit provides predictable phase-locked loop output phase synchronization with an input clock.

    Abstract translation: 一种用于使输出信号的边沿与输入信号的边沿同步的锁相环电路。 电路检测输入时钟信号的边沿和输出信号上的相应边沿。 如果输出信号边沿与输入时钟边沿不同相，则电路将输出信号移位180度，以有效地产生单个双长度时钟相位。 同步锁相环电路提供与输入时钟的可预测的锁相环输出相位同步。

    Phase-locked loop circuit and radio communication apparatus using the same
    88.
    发明申请
    Phase-locked loop circuit and radio communication apparatus using the same 有权
    锁相环电路和使用其的无线电通信装置

    公开(公告)号：US20040032901A1

    公开(公告)日：2004-02-19

    申请号：US10641136

    申请日：2003-08-15

    Inventor： Taizo Yamawaki ,  Masaru Kokubo ,  Tomio Furuya ,  Kazuo Watanabe ,  Julian Hildersley

    IPC: H04B001/38 ,  H04L005/16

    CPC classification number: H03L7/085 ,  H03L7/10 ,  H03L7/183 ,  H03L2207/12 ,  H04B1/403 ,  H04B1/408

    Abstract: A communication apparatus includes a phase-locked loop circuit which receives a first signal having a frequency and converts it into an output signal having a transmission frequency and includes a current output type phase comparator which converts a phase difference between the first signal and a second signal into a current signal, a low pass filter which filters the current signal of the current output type phase comparator to produce an output signal a voltage controlled oscillator which produces an output signal having a transmission frequency corresponding to the output signal of the low pass filter the output signal of the voltage controlled oscillator constituting the output signal of the phase-locked loop circuit, a frequency converter which frequency-converts the output signal of the voltage controlled oscillator to produce the second signal, and a current source which supplies a current to an input of the low pass filter.

    Abstract translation: 通信装置包括锁相环电路，其接收具有频率的第一信号并将其转换为具有发送频率的输出信号，并且包括电流输出型相位比较器，其转换第一信号和第二信号之间的相位差 将低通滤波器滤波电流输出型相位比较器的电流信号以产生输出信号，该压控振荡器产生具有与低通滤波器的输出信号对应的发送频率的输出信号， 构成锁相环电路的输出信号的压控振荡器的输出信号，对压控振荡器的输出信号进行频率转换以产生第二信号的频率转换器，以及向 输入低通滤波器。

    Precision jitter-free frequency synthesis
    89.
    发明申请
    Precision jitter-free frequency synthesis 有权
    精密无抖动频率合成

    公开(公告)号：US20040008805A1

    公开(公告)日：2004-01-15

    申请号：US10376453

    申请日：2003-02-26

    Applicant: Texas Instruments Incorporated

    Inventor： Liming Xiu ,  Zhihong You

    IPC: H03D003/24

    CPC classification number: H03L7/183 ,  H03L7/0996

    Abstract: An electronic system (10) includes a phase-locked loop (30) and a frequency synthesis circuit (20), for generating a jitter-free output clock (CLK1, CLK2) at a desired frequency. The phase-locked loop (30) includes a voltage-controlled oscillator (37) that produces a number (N) of equally spaced clock phases at a frequency (fVCO) that depends also upon a programmable feedback frequency divider (38) and a prescale divider (32). The frequency synthesis circuit (20) generates the output clock (CLK1, CLK2) at a frequency under the control of a frequency select word (FREQ) that indicates the number of clock phases between successive clock edges. A central processing unit (12), either itself or from a look-up table (13), generates a feedback divide integer (M) and the frequency select word (FREQ) according to a desired frequency (null), by way of a minimization of the frequency error. The frequency of the output clock (CLK1, CLK2) can be generated in a jitter-free manner, since only integer values are used in the frequency synthesis circuit (20), at relatively low frequency error.

    Abstract translation: 电子系统（10）包括锁相环（30）和频率合成电路（20），用于以期望的频率产生无抖动的输出时钟（CLK1，CLK2）。 锁相环（30）包括压控振荡器（37），该压控振荡器产生频率（fVCO）的等距间隔时钟相位数（N），该频率依赖于可编程反馈分频器（38）和预分频器 分频器（32）。 频率合成电路（20）在频率选择字（FREQ）的控制下以指示连续的时钟边沿之间的时钟相位数的频率产生输出时钟（CLK1，CLK2）。 本身或来自查找表（13）的中央处理单元（12）根据期望频率（f）产生反馈除法整数（M）和频率选择字（FREQ），借助于 最小化频率误差。 输出时钟（CLK1，CLK2）的频率可以以无抖动的方式产生，因为在频率合成电路（20）中以相对低的频率误差仅使用整数值。

    Use of configurable capacitors to tune a self based phase locked loops
    90.
    发明申请
    Use of configurable capacitors to tune a self based phase locked loops 有权
    使用可配置电容调谐自相位锁相环

    公开(公告)号：US20030206066A1

    公开(公告)日：2003-11-06

    申请号：US10138391

    申请日：2002-05-03

    Inventor： Michael Harwood

    IPC: H03L007/00

    CPC classification number: H03L7/093 ,  H03L7/0893 ,  H03L7/183 ,  H03L2207/04 ,  H03L2207/06

    Abstract: A phase locked loop (PLL) comprising an input, an output, a charge generator, a low pass filter 3, an oscillator 4 and a frequency divider 5. The frequency divider 5 has an input coupled to the output of the PLL and an output coupled to an input of the charge generator. The frequency at the output of the frequency divider 5 is equal to the frequency at the input of the frequency divider divided by a selectable divider ratio N. The PLL has a damping factor z and a bandwidth to compare frequency ratio null3/nullref. The low pass filter 3 has a first capacitor for integrating the charge produced by the charge generator. The capacitance of that first capacitor is arranged to be proportional to the divider ratio N so that the damping factor z and the bandwidth to compare frequency ratio null3/nullref are substantially independent of the divider ratio N.

    Abstract translation: 包括输入，输出，电荷发生器，低通滤波器3，振荡器4和分频器5的锁相环（PLL）。分频器5具有耦合到PLL的输出的输入和输出 耦合到电荷发生器的输入。 分频器5的输出端的频率等于分频器输入端的频率除以可选择的分频比N. PLL具有阻尼系数z和带宽以比较频率比ω3/ωgaref。 低通滤波器3具有用于对由电荷发生器产生的电荷进行积分的第一电容器。 该第一电容器的电容被布置成与分频比N成比例，使得阻尼因子z和比较频率比ω3/ωgaref的带宽基本上与分频比N无关。

Patent Agency Ranking