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公开(公告)号：US5576664A
公开(公告)日：1996-11-19
申请号：US556882
申请日：1995-11-02
申请人： Barry W. Herold , Scott R. Humphreys , Phillip Johnson , Raymond L. Barrett, Jr. , Grazyna A. Pajunen
发明人： Barry W. Herold , Scott R. Humphreys , Phillip Johnson , Raymond L. Barrett, Jr. , Grazyna A. Pajunen
摘要： A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled oscillator (232). The accumulator (219) is connected to the phase detector (202) and a reference signal (136) for calculating an accumulator output value equal to a first sum of a current sample generated by the phase detector (202), and all of the plurality of discrete phase error samples produced prior to the current sample. The adder (227) is connected to the phase detector (202) and the accumulator (219) for forming a second sum of the current sample and the accumulator output value. The controlled oscillator (232) receives the second sum, which is utilized for controlling the controlled oscillator (232).
摘要翻译： 通信接收器（100）采用离散时间数字锁相环（142）来保持锁定到参考信号（136）的生成信号（144）。 离散时间数字锁相环（142）包括相位检测器（202），累加器（219），加法器（227）和受控振荡器（232）。 累加器（219）连接到相位检测器（202）和参考信号（136），用于计算等于由相位检测器（202）生成的当前采样的第一和的累加器输出值，并且所有多个 在当前样本之前产生的离散相位误差样本。 加法器（227）连接到相位检测器（202）和累加器（219），用于形成当前采样和累加器输出值的第二和。 受控振荡器（232）接收用于控制受控振荡器（232）的第二和。
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公开(公告)号：US5535067A
公开(公告)日：1996-07-09
申请号：US400621
申请日：1995-03-06
申请人： Matthew W. Rooke
发明人： Matthew W. Rooke
CPC分类号： H03L7/181 , G11B20/1403 , H03L7/085 , G11B20/1258
摘要： The invention is a write clock generator circuit adapted for use in disk drives having either dedicated servo or sector servo architecture. A high frequency write clock signal is generated from a relatively low frequency reference signal synchronized to disk rotation. The reference signal may originate from a number of sources, including a dedicated servo pattern, a sector servo pattern, any index pattern, or a spindle pulse. A clock generates a clock signal having a predetermined number of cycles for each reference period. A counter coupled to the output of the clock counts the number of clock cycles generated for each reference period. The number of cycles is then compared to an expected number corresponding to a desired clock frequency. If the compared numbers are not the same, an error signal is generated. Control logic receives the error signal and the reference signal, and generates an appropriate control signal. The control signal is coupled to the clock and thereby adjusts the write clock signal frequency.
摘要翻译： 本发明是适用于具有专用伺服或扇区伺服架构的磁盘驱动器中的写时钟发生器电路。 从与盘旋转同步的相对低频参考信号产生高频写入时钟信号。 参考信号可以源自多个源，包括专用伺服模式，扇区伺服模式，任何索引模式或主轴脉冲。 时钟为每个参考周期产生具有预定数量的周期的时钟信号。 耦合到时钟输出的计数器对每个参考周期产生的时钟周期数进行计数。 然后将周期数与期望的时钟频率对应的期望数进行比较。 如果比较数不相同，则产生误差信号。 控制逻辑接收误差信号和参考信号，并产生适当的控制信号。 控制信号耦合到时钟，从而调整写入时钟信号频率。
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公开(公告)号：US5521556A
公开(公告)日：1996-05-28
申请号：US379049
申请日：1995-01-27
CPC分类号： H03K3/0315 , H03L7/097 , H03L7/181
摘要： A monolithic frequency converter using a feedback control loop generates a source of synthesized frequency signals over a wide dynamic range based on a timing source such as a crystal oscillator or an external frequency source. The frequency converter includes a controlled oscillator, a frequency counter, a timing signal generator and, connected between the frequency counter and the controlled oscillator, a digital to analog converter and a difference integrator. The controlled oscillator generates a clock signal at a frequency controlled by an electrical signal. The difference integrator is connected to an input signal terminal and connected to the timing signal generator. The difference integrator determines a difference signal between the input signal and a signal operated upon by the digital to analog converter and integrates the difference signal under control of a timing signal generated by the timing signal generator. The frequency converter has a highly linear transfer function which is established by the resolution of a frequency counter. For example, a transfer function having approximately 0.1% accuracy in linearity is achieved using a 10-bit resolution frequency counter. Using indirect frequency synthesis, the controlled oscillator generates precisely controlled timing signals.
摘要翻译： 使用反馈控制回路的单片变频器基于诸如晶体振荡器或外部频率源的定时源在宽动态范围上产生合成频率信号源。 变频器包括受控振荡器，频率计数器，定时信号发生器，并连接在频率计数器和受控振荡器之间，数模转换器和差分积分器。 受控振荡器以由电信号控制的频率产生时钟信号。 差分积分器连接到输入信号端并连接到定时信号发生器。 差分积分器确定输入信号和由数模转换器操作的信号之间的差分信号，并在由定时信号发生器产生的定时信号的控制下对差分信号进行积分。 变频器具有通过频率计数器的分辨率建立的高度线性传递函数。 例如，使用10位分辨率频率计数器实现线性精度约为0.1％的传递函数。 使用间接频率合成，受控振荡器产生精确控制的定时信号。
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公开(公告)号：US5406228A
公开(公告)日：1995-04-11
申请号：US274011
申请日：1994-07-12
申请人： Chinh L. Hoang
发明人： Chinh L. Hoang
CPC分类号： H03K3/0315 , H03K3/354 , H03L7/085 , H03L7/0995
摘要： An oscillator system and method in which a time period (inverse of frequency) of a multi-stage ring oscillator (ROSC) is adjusted by a bias current which controls the charging and discharging times of respective capacitors (e.g., interelectrode capacities) within each stage. The time periods of the unadjusted oscillator are counted along with the time periods of a reference clock over a same period of time and a count difference between the two counts is determined. The count difference is applied by a logic circuit in accordance with an algorithm relating count differences to incremental bias current levels to adjust the frequency of the oscillator. The logic circuit generates digital gate signals corresponding to the count difference and these signals automatically select the bias current level needed to bring the oscillator frequency into close agreement with the reference clock frequency. The digital gate signals are stored in a non-volatile memory so that the oscillator will continue to operate at the adjusted frequency (i.e., that of the reference clock) even if the reference clock is no longer present and power is temporarily removed. The oscillator system is well suited for implementation by complementary metal oxide semiconductor (CMOS) technology as part of an integrated circuit (IC).
摘要翻译： 通过控制各电容器（例如，电极间电容）的充放电时间的偏置电流来调整多级环形振荡器（ROSC）的时间周期（频率的倒数）的振荡器系统和方法 。 未调整的振荡器的时间周期与同一时间段的参考时钟的时间周期一起计数，并且确定两个计数之间的计数差。 根据将计数差与增量偏置电流电平相关联的算法由逻辑电路施加计数差，以调整振荡器的频率。 逻辑电路产生对应于计数差的数字门信号，这些信号自动选择使振荡器频率与参考时钟频率密切相关所需的偏置电流电平。 数字门信号被存储在非易失性存储器中，使得即使参考时钟不再存在并且功率被暂时移除，振荡器将继续以调整频率（即参考时钟的频率）工作。 振荡器系统非常适用于作为集成电路（IC）的一部分的互补金属氧化物半导体（CMOS）技术的实现。
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公开(公告)号：US5381181A
公开(公告)日：1995-01-10
申请号：US60923
申请日：1993-05-13
申请人： Michael S. Deiss
发明人： Michael S. Deiss
IPC分类号： H04B1/66 , G06T9/00 , H03L7/085 , H03L7/181 , H04J3/00 , H04L7/00 , H04L7/033 , H04L12/70 , H04L13/08 , H04N7/08 , H04N7/081 , H04N7/24 , H04N7/62 , H04N11/04 , H04N19/00 , H04N19/89 , H04N21/236 , H04N21/43 , H04N21/434 , H04N7/13
CPC分类号： H04N19/61 , H03L7/085 , H03L7/181 , H04N19/00 , H04N21/23608 , H04N21/23614 , H04N21/4305 , H04N21/4348 , H04N19/70
摘要： Apparatus for developing synchronization of an intermediate layer of signal such as the transport or multiplex layer of a multi-layered compressed video signal, includes at the encoding end of the system a modulo K counter which is clocked responsive to a system clock, and the count valued is embedded in the signal at the transport layer according to a predetermined schedule. At the receiving end of the system a similar counter is responsive to a controlled receiver clock signal and the count value of this counter is sampled at the arrival of the count values embedded in the transport layer. The differences of successive sampled count values of the receiver counter are compared with the differences of corresponding successive values of the embedded count values in the transport layer to provide a signal to control the receiver clock signal.
摘要翻译： 用于开发诸如多层压缩视频信号的传输层或复用层之类的信号中间层的同步的装置包括在系统的编码端，响应于系统时钟计时的模K计数器，并且计数 根据预定的时间表将价值嵌入在传输层的信号中。 在系统的接收端，类似的计数器响应受控接收器时钟信号，并且在嵌入在传输层中的计数值的到达时对该计数器的计数值进行采样。 将接收机计数器的连续采样计数值的差异与传输层中嵌入的计数值的相应连续值的差异进行比较，以提供控制接收机时钟信号的信号。
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86.发明授权Delay circuit having one of a plurality of delay lines which may be selected to provide an operation of a ring oscillator 失效延迟电路具有多个延迟线中的一个可被选择以提供环形振荡器的操作
公开(公告)号：US5087842A
公开(公告)日：1992-02-11
申请号：US341250
申请日：1989-04-19
CPC分类号： H03L7/0805 , H03K5/131 , H03K5/133 , H03K5/135 , H03L7/0995 , H03L7/181
摘要： The delay period of a delay circuit is maintained, over time, near to a desired delay, by generating information representative of the present delay period of the delay circuit, and altering the delay period, from time to time during operation, based on the present delay information and the desired delay. The present delay is measured by a reference circuit having a delay characteristic corresponding to the delay characteristic of the delay circuit. Both the reference and multiple delay circuits are formed with the same configuration on a single integrated circuit.
摘要翻译： 延迟电路的延迟时间通过产生表示延迟电路的当前延迟周期的信息，并且随着时间的推移而接近期望的延迟，并且在操作期间根据当前的时间改变延迟周期 延迟信息和所需的延迟。 本延迟由具有与延迟电路的延迟特性对应的延迟特性的参考电路测量。 参考电路和多个延迟电路都在单个集成电路上以相同的配置形成。
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公开(公告)号：US4901027A
公开(公告)日：1990-02-13
申请号：US284691
申请日：1988-12-15
申请人： Hitoshi Kitayoshi
发明人： Hitoshi Kitayoshi
CPC分类号： H03L7/00 , H03B27/00 , H03L7/0812
摘要： In a phase accumulation type signal generatorm when an adder of a phase accumulator yields a carry output, a difference circuit generates an analog voltage V.sub.1 =a.sub.2 (n-k.sub.s) which is in proportion to the difference between the output k.sub.s of the adder and a phase add amount n. A ramp function voltage generator generates a ramp function voltage V(t)=nfa.sub.1 a.sub.3 t/cm which is in proportion to the product of the frequency f/m of a clock and the phase add amount n. The analog voltage and the ramp function voltage are compared by a comparator, which outputs a synchronization pulse when they agree with each other.
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公开(公告)号：US4805198A
公开(公告)日：1989-02-14
申请号：US51985
申请日：1987-05-19
CPC分类号： G06F5/10 , H03L7/085 , H03L7/0991 , H03L7/181 , H04J3/0626 , G06F2205/061
摘要： A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.
摘要翻译： 时钟倍增器/抖动衰减器电路提供稳定的时钟，其是外部数字数据流的平均频率的多个频率。 外部数据以其自己的时钟速率写入FIFO的连续存储单元，并以由分频稳定时钟形成的内部时钟信号的速率读出FIFO。 以周期性的时间间隔确定要写入的单元和读出的单元的相对位置，并且这些相对位置用于调整产生稳定时钟的内部振荡器的频率。 数字数据流上的瞬时抖动被FIFO吸收。
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89.发明授权
公开(公告)号：US4646030A
公开(公告)日：1987-02-24
申请号：US835583
申请日：1986-03-03
申请人： Allen L. Hollister
发明人： Allen L. Hollister
CPC分类号： H03K3/03 , H03K7/06 , H03L7/0995 , H03L7/181 , Y10S331/03
摘要： An oscillator produces an output signal which is frequency locked to a reference signal but phased locked to a triggering signal. The oscillator includes a NOR gate having its output fed back to one of its inputs through a programmable delay circuit while the triggering signal is applied to another of its inputs. When enabled by the triggering signal, the output signal of the NOR gate oscillates at a frequency inversely proportional to the delay time of the delay circuit. The delay time is controlled by a control circuit which counts NOR gate output signal cycles occurring during a predetermined number of reference signal cycles and increments the delay time when the count is higher than expected for an oscillator output signal of a desired frequency and decrements the delay time when the count is lower than expected.
摘要翻译： 振荡器产生频率锁定到参考信号但被锁相到触发信号的输出信号。 振荡器包括NOR门，其NOR输出端通过可编程延迟电路反馈到其输入端之一，同时将触发信号施加到其另一个输入端。 当触发信号使能时，NOR门的输出信号以与延迟电路的延迟时间成反比的频率振荡。 延迟时间由控制电路控制，该控制电路在预定数量的参考信号周期期间计数NOR门输出信号周期，并且当计数高于期望频率的振荡器输出信号的预期时延迟延迟时间，并且减小延迟 计数低于预期的时间。
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公开(公告)号：US4520327A
公开(公告)日：1985-05-28
申请号：US388630
申请日：1982-06-15
申请人： Roland Myers
发明人： Roland Myers
摘要： A variable frequency oscillator 10 has an output frequency Fo responsive to a voltage input Vo derived from an analogue integrator 11 controlled by potentiometer 15, 16, the frequency Fo being displayed on frequency meter 19 having a ghost least significant digit. A converter 24 responds to the digit of a digital output fed to a digital to analogue converter 20 providing an error voltage Ve whose magnitude is proportional to the deviation of the digit from a datum, e.g. 5, and whose polarity depends on whether the deviation is + or -. The voltage Ve is also fed to the integrator 11 to control the voltage Vo.An arrangement is also described in which the voltage Ve is derived from the divider chain of a gate period generator controlling a frequency counter whose input is Fo.
摘要翻译： 可变频率振荡器10具有响应于由电位计15,16控制的模拟积分器11导出的电压输入Vo的输出频率Fo，频率仪表19上显示的频率Fo具有重影最小有效数字。 A转换器24响应馈送到数模转换器20的数字输出的数字，提供误差电压Ve，其幅度与数字与数据的偏差成比例，例如。 5，其极性取决于偏差是+还是 - 。 电压Ve也被馈送到积分器11以控制电压Vo。 还描述了其中电压Ve从控制输入为Fo的频率计数器的门限周期发生器的分频器导出的装置。
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