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公开(公告)号：US08885081B2
公开(公告)日：2014-11-11
申请号：US13408508
申请日：2012-02-29
Applicant: Yoshio Hagihara
Inventor： Yoshio Hagihara
Abstract: In an A/D converter, a ramp unit generates a reference signal that increases or decreases over time. A comparison unit starts a comparison process of comparing an analog signal to the reference signal at a timing related to input of the analog signal and ends the comparison process at a timing at which the reference signal satisfies a predetermined condition with respect to the analog signal. A VCO includes a plurality of delay units having the same configuration and starts a transition process at a timing related to the start of the comparison process. A count unit counts a clock from the VCO. A low-order latch unit latches a low-order logic state, which is a logic state of the plurality of delay units, at a first timing related to the end of the comparison process. A high-order latch unit latches a high-order logic state.
Abstract translation: 在A / D转换器中，斜坡单元产生随时间增加或减小的参考信号。 比较单元在与模拟信号的输入相关的定时开始比较模拟信号与参考信号的比较处理，并且在参考信号相对于模拟信号满足预定条件的定时结束比较处理。 VCO包括具有相同配置的多个延迟单元，并且在与开始比较处理相关的定时处开始转换处理。 计数单元计算来自VCO的时钟。 在与比较处理结束相关的第一定时，低位锁存单元锁存作为多个延迟单元的逻辑状态的低阶逻辑状态。 高位锁存单元锁存高阶逻辑状态。
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公开(公告)号：US08872089B2
公开(公告)日：2014-10-28
申请号：US13638258
申请日：2011-03-29
Applicant: Keisuke Korekado , Tomoyuki Kamiyama , Yoichi Nishimura
Inventor： Keisuke Korekado , Tomoyuki Kamiyama , Yoichi Nishimura
Abstract: Disclosed is a solid-state imaging device capable of calculating the difference in charge obtained by photoelectric conversion, and capable of a high level of integration. A solid-state imaging device is provided with an AD converter which is provided with: a first comparator which outputs a signal corresponding to a first analog signal of a first pixel by comparing said first analog signal with a reference voltage supplied from the reference voltage generation unit which generates a reference voltage which gradually changes; a second comparator which outputs a signal corresponding to a second analog signal of a second pixel by comparing said second analog signal with the reference voltage supplied by the reference voltage generation unit; a difference circuit which finds the difference between the signal corresponding to said first analog signal and the signal corresponding to said second analog signal and outputs a difference signal; and a counter circuit which counts the number of pulses in a pulse sequence corresponding to the aforementioned difference signal and converts said difference signal into a digital signal.
Abstract translation: 公开了能够计算通过光电转换获得的电荷差异并且能够高集成度的固态成像装置。 固态成像装置设置有AD转换器，其具有：第一比较器，其通过将所述第一模拟信号与从参考电压产生提供的参考电压进行比较来输出与第一像素的第一模拟信号相对应的信号 产生逐渐变化的参考电压的单元; 第二比较器，通过将所述第二模拟信号与由参考电压产生单元提供的参考电压进行比较来输出与第二像素的第二模拟信号相对应的信号; 差分电路，其找到与所述第一模拟信号相对应的信号与对应于所述第二模拟信号的信号之间的差，并输出差分信号; 以及计数器电路，对与上述差分信号相对应的脉冲序列中的脉冲数进行计数，并将所述差分信号转换为数字信号。
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83.发明授权Ramp signal output circuit, analog-to-digital conversion circuit, imaging device, method for driving ramp signal output circuit, method for driving analog-to-digital conversion circuit, and method for driving imaging device 有权斜坡信号输出电路，模数转换电路，成像装置，用于驱动斜坡信号输出电路的方法，驱动模数转换电路的方法和驱动成像装置的方法公开(公告)号：US08760213B2
公开(公告)日：2014-06-24
申请号：US13628365
申请日：2012-09-27
Applicant: Canon Kabushiki Kaisha
Inventor： Kazuhiro Saito , Hiroki Hiyama , Tetsuya Itano , Kohichi Nakamura
CPC classification number: H03K4/06 , H03K3/0231 , H03K4/08 , H03K4/50 , H03M1/123 , H03M1/50 , H03M1/56 , H04N5/378
Abstract: A circuit configured to output a ramp signal having a potential varying depending on time includes a voltage supply unit configured to supply a plurality of voltages having different amplitudes, a current supply unit, an integration circuit configured to output the ramp signal, and a capacitive element. The voltage supply unit is connected to one terminal of the capacitive element. The integration circuit and the current supply unit are connected to another terminal of the capacitive element.
Abstract translation: 配置为输出具有随时间变化的电位的斜坡信号的电路包括：电压供给单元，被配置为提供具有不同幅度的多个电压;电流供应单元，被配置为输出斜坡信号的积分电路;以及电容元件 。 电压供应单元连接到电容元件的一个端子。 集成电路和电流源单元连接到电容元件的另一个端子。
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公开(公告)号：US08717220B2
公开(公告)日：2014-05-06
申请号：US13306868
申请日：2011-11-29
Applicant: R. Jacob Baker
Inventor： R. Jacob Baker
IPC: H03M1/56
Abstract: Methods for reading a data location coupled to an electrical conductor. A counter receives a signal from an analog-to-digital converter coupled to the electrical conductor. The counter produces two or more counts, and in some embodiments, the counts are based in part on a variable reference voltage. An interfuser may be coupled to an output of the counter. The interfuser receives the two or more counts from the counter and reads data conveyed by the data location based on the two or more counts.
Abstract translation: 读取耦合到电导体的数据位置的方法。 计数器从耦合到电导体的模数转换器接收信号。 计数器产生两个或多个计数，并且在一些实施例中，计数部分地基于可变参考电压。 接口用户可以耦合到计数器的输出。 接口用户从计数器接收两个或多个计数，并且基于两个或更多个计数读取由数据位置传送的数据。
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公开(公告)号：US08659465B2
公开(公告)日：2014-02-25
申请号：US13293969
申请日：2011-11-10
Applicant: Laurent Simony , Benoît Deschamps , Alexandre Cellier , Frédéric Barbier
Inventor： Laurent Simony , Benoît Deschamps , Alexandre Cellier , Frédéric Barbier
IPC: H03M1/56
Abstract: A method of analog to digital voltage conversion including: generating a quadratic signal based on an analog time varying reference signal; generating a ramp signal based on the quadratic signal; and converting an analog input voltage to a digital output value based on a time duration determined by a comparison of the analog input voltage with the ramp signal.
Abstract translation: 一种模数电压转换方法，包括：基于模拟时变参考信号产生二次信号; 基于二次信号产生斜坡信号; 并且基于通过模拟输入电压与斜坡信号的比较确定的持续时间，将模拟输入电压转换为数字输出值。
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Patent Agency Ranking
公开(公告)号：US08659360B2
公开(公告)日：2014-02-25
申请号：US13338390
申请日：2011-12-28
Applicant: Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
Inventor： Petri Heliö , Petri Korpi , Niko Mikkola , Paavo Väänänen , Sami Vilhonen
CPC classification number: H03L7/06 , G04F10/005 , G04F10/105
Abstract: The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load.
Abstract translation: 这里公开的电荷数字计时装置和方法估计两个信号之间的经过时间，例如起始信号和停止信号。 为此，至少电容性负载以已知电流充电以产生负载电压。 随后，第一电压以与多个已知电容相关联的多个离散电压阶跃斜坡，直到斜坡电压相对于第二电压满足预定标准。 经过的时间由离散的电压阶跃确定，第一和第二电压之一，已知电流和已知的容性负载。
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87.发明授权公开(公告)号：US08520110B2
公开(公告)日：2013-08-27
申请号：US13336759
申请日：2011-12-23
Applicant: Hirotaka Kitami , Kenichi Okumura
Inventor： Hirotaka Kitami , Kenichi Okumura
CPC classification number: H04N5/378 , H03M1/1225 , H04N5/23245 , H04N5/343 , H04N5/347
Abstract: A solid-state imaging device and an imaging apparatus are provided. The solid-state imaging device performs an AD conversion in a column parallel for an analog pixel signal outputted from each of pixels disposed in a two-dimensional matrix shape. The solid-state imaging device includes: an AD conversion unit including a plurality of pixel signal accumulating units; a first switching unit for disconnecting parallel connection of a second pixel signal accumulating unit other than a first pixel signal accumulating unit which is one of the plurality of pixel signal accumulating units; and a second switching unit for connecting the second pixel signal accumulating unit to a pixel signal line of a second pixel adjacent to the first pixel in a row direction, when parallel connection of the second pixel signal accumulating unit is disconnected by the first switching unit.
Abstract translation: 提供固态成像装置和成像装置。 固态成像装置对从以二维矩阵形状布置的每个像素输出的模拟像素信号并行的列进行AD转换。 固态成像装置包括：AD转换单元，包括多个像素信号累积单元; 第一切换单元，用于断开除了作为所述多个像素信号累加单元之一的第一像素信号累积单元以外的第二像素信号累积单元的并联连接; 以及第二切换单元，用于当所述第二像素信号存储单元的并行连接被所述第一切换单元断开时，将所述第二像素信号累积单元连接到与所述第一像素相邻的第二像素的像素信号线的行方向。
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公开(公告)号：US20130063295A1
公开(公告)日：2013-03-14
申请号：US13610062
申请日：2012-09-11
Applicant: Yoshio Hagihara
Inventor： Yoshio Hagihara
IPC: H03M1/56 , H01L27/146
Abstract: In an A/D conversion circuit and an imaging device, an upper counter acquires a first upper count value by performing counting using one output signal, which constitutes a first lower phase signal output from a delay circuit, as a count clock. After values of bits constituting the first upper count value are inverted, the upper counter acquires a second upper count value by performing counting using one output signal, which constitutes a second lower phase signal output from the delay circuit, as a count clock, and further performing counting based on an upper count clock output from a lower counter. A modification unit modifies a logic state of a count clock to a predetermined state when the count clock of the upper counter is switched.
Abstract translation: 在A / D转换电路和成像装置中，上计数器通过使用构成从延迟电路输出的第一下相位信号的一个输出信号作为计数时钟进行计数来获取第一上计数值。 在构成第一上计数值的位的值被反转之后，上计数器通过使用构成从延迟电路输出的第二较低相位信号的一个输出信号作为计数时钟进行计数来获取第二上计数值，并且进一步 基于从下计数器输出的上计数时钟进行计数。 当切换上位计数器的计数时钟时，修改单元将计数时钟的逻辑状态修改为预定状态。
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公开(公告)号：US08395540B2
公开(公告)日：2013-03-12
申请号：US13213099
申请日：2011-08-19
Applicant: Qi-Long Yu , Jun Zhang , Tsung-Jen Chuang , Shih-Fang Wong
Inventor： Qi-Long Yu , Jun Zhang , Tsung-Jen Chuang , Shih-Fang Wong
IPC: H03M1/56
CPC classification number: H03M1/56
Abstract: An ADC includes an analog signal input port for receiving analog signals, a reference voltage generation circuit for producing a reference voltage, a controllable switch, a control unit including a counter, an integral circuit, and a comparison circuit. The control unit outputs an on or off signal to turn on or turn off the controllable switch, the counter starts to count when the control unit outputs the off signal. The integral circuit executes an integral action to integrate the reference voltage and output a voltage enhanced gradually when the controllable switch is turned off. The comparison circuit outputs an interrupt signal to cause the counter to stop counting when comparing the voltage output by the integral circuit is higher than the voltage of the analog signals. The control unit determines a digital value corresponding to the analog signals according to a count value of counted by the counter.
Abstract translation: ADC包括用于接收模拟信号的模拟信号输入端口，用于产生参考电压的参考电压产生电路，可控开关，包括计数器，积分电路和比较电路的控制单元。 控制单元输出开启或关闭信号以打开或关闭可控开关，当控制单元输出关闭信号时，计数器开始计数。 积分电路执行积分动作以集成参考电压，并在可控开关关闭时逐渐输出增强的电压。 当比较积分电路的电压高于模拟信号的电压时，比较电路输出中断信号使计数器停止计数。 控制单元根据由计数器计数的计数值来确定与模拟信号相对应的数字值。
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90.发明授权Double data rate (DDR) counter, analog-to-digital converter (ADC) using the same, CMOS image sensor using the same and methods in DDR counter, ADC and CMOS image sensor 有权双数据速率（DDR）计数器，使用相同的模数转换器（ADC），使用相同的CMOS图像传感器和DDR计数器，ADC和CMOS图像传感器公开(公告)号：US08395539B2
公开(公告)日：2013-03-12
申请号：US12632168
申请日：2009-12-07
Applicant: Yong Lim , Kyoung-Min Koh , Kyung-Min Kim
Inventor： Yong Lim , Kyoung-Min Koh , Kyung-Min Kim
IPC: H03M1/56
CPC classification number: H04N5/378 , H03M1/0607 , H03M1/123 , H03M1/1295 , H03M1/56 , H04N5/3698
Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The counter includes at least one second stage for generating another bit of the value in the counter. An input clock signal is applied to a data input of the first stage and a clock input of the second stage.
Abstract translation: 在例如CMOS图像传感器和方法中的例如模数转换中使用的双数据速率（DDR）计数器和计数方法中，计数器的第一级产生最低有效位（LSB） ）在柜台的价值。 计数器包括用于在计数器中产生值的另一位的至少一个第二级。 输入时钟信号被施加到第一级的数据输入端和第二级的时钟输入端。
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