利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

2378 条记录 (耗时 0.06 秒)

    Symbol mapping for binary coding
    82.
    发明授权
    Symbol mapping for binary coding 有权
    二进制编码的符号映射

    公开(公告)号：US09209834B2

    公开(公告)日：2015-12-08

    申请号：US13907737

    申请日：2013-05-31

    申请人： BROADCOM CORPORATION

    发明人： Tak K. Lee ,  Ba-Zhong Shen ,  Kelly Brian Cameron ,  Hau Thien Tran

    IPC分类号： H03M13/00 ,  G06F11/00 ,  H03M13/05 ,  H04L27/34 ,  H04L27/36

    CPC分类号： H04L27/3438 ,  H03M13/05 ,  H03M13/37 ,  H03M13/617 ,  H04L1/0041 ,  H04L27/362

    摘要： The present disclosure presents symbol mapping for any desired error correction code (ECC) and/or uncoded modulation. A cross-shaped constellation is employed to perform symbol mapping. The cross-shaped constellation is generated from a rectangle-shaped constellation. Considering the rectangle-shaped constellation and its left hand side, a first constellation point subset located along that left hand side are moved to be along a top of the cross-shaped constellation while a second constellation point subset located along that left hand side are moved to be along a bottom of the cross-shaped constellation. For example, considering an embodiment having four constellation point subsets along the left hand side of the rectangle-shaped constellation, two of those subsets are moved to be along the top of the cross-shaped constellation while two other subsets of the constellation points along the left hand side are moved to be along the bottom of the cross-shaped constellation.

    摘要翻译： 本公开提供了用于任何期望的纠错码（ECC）和/或未编码调制的符号映射。 采用十字形星座进行符号映射。 十字形星座由矩形星座产生。 考虑到矩形星座及其左手侧，沿着左手侧定位的第一星座点子集沿着十字形星座的顶部移动，而沿着该左手侧的第二星座点子集被移动 沿着十字形星座的底部。 例如，考虑到具有沿着矩形星座的左手侧的四个星座点子集的实施例，这些子集中的两个被移动为沿着十字形星座的顶部移动，而星座点的另外两个子集沿着 左手侧被移动到十字形星座的底部。

    COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION
    84.
    发明申请
    COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION 审中-公开
    具有错误校正的复合半导体存储器件

    公开(公告)号：US20150309867A1

    公开(公告)日：2015-10-29

    申请号：US14795114

    申请日：2015-07-09

    申请人： Conversant Intellectual Property Management Inc.

    发明人： Jin-Ki KIM

    IPC分类号： G06F11/10 ,  H03M13/00 ,  H03M13/05

    CPC分类号： G06F11/1044 ,  G06F11/1048 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/611

    摘要： A composite semiconductor memory device, comprising: a plurality of nonvolatile memory devices; and an interface device connected to the plurality of nonvolatile memory devices and for connection to a memory controller, the interface device comprising an error correction coding (ECC) engine. Also, a memory system, comprising: a memory controller; and at least one composite semiconductor memory device configured for being written to and read from by the memory controller and comprising a built-in error correction coding (ECC) engine. Also, a memory system, comprising: a composite semiconductor memory device comprising a plurality of nonvolatile memory devices; and a memory controller connected to the at least one composite semiconductor memory device, for issuing read and write commands to the composite semiconductor memory device to cause data to be written to or read from individual ones of the nonvolatile memory devices; the composite semiconductor memory device providing error-free writing and reading of the data.

    摘要翻译： 一种复合半导体存储器件，包括：多个非易失性存储器件; 以及连接到所述多个非易失性存储器件并且用于连接到存储器控制器的接口设备，所述接口设备包括纠错编码（ECC）引擎。 另外，一种存储器系统，包括：存储器控制器; 以及至少一个复合半导体存储器件，被配置为被存储器控制器写入和读出，并且包括内置纠错编码（ECC）引擎。 另外，一种存储系统，包括：复合半导体存储器件，其包括多个非易失性存储器件; 以及存储器控制器，连接到所述至少一个复合半导体存储器件，用于向所述复合半导体存储器件发出读取和写入命令，以使数据被写入或从所述非易失性存储器件中的各个写入; 所述复合半导体存储器件提供无错误的写入和读取数据。

    Reed-solomon decoder
    85.
    发明授权
    Reed-solomon decoder 有权
    里德独奏解码器

    公开(公告)号：US09166623B1

    公开(公告)日：2015-10-20

    申请号：US13803919

    申请日：2013-03-14

    申请人： PMC-SIERRA US, INC.

    发明人： Stephen Bates ,  Peter Graumann ,  Phil Northcott

    IPC分类号： H03M13/00 ,  H03M13/05 ,  H03M13/15

    CPC分类号： H03M13/1515 ,  H03M13/153 ,  H03M13/154 ,  H03M13/1555 ,  H03M13/373 ,  H03M13/45

    摘要： A system and method of decoding a Reed-Solomon code using a Reed-Solomon decoder comprising an erasure location selector, multiple syndrome formers and multiple Berlekamp-Massey decoders that share a single error correction unit, and means for selecting a Berlekamp-Massey decoder output as the input to the error correction unit. The method improves the bit error rate performance of the Reed-Solomon decoder compared to known hard-decision and soft-decision Reed-Solomon decoders. The Reed-Solomon decoder also provides hardware area and power savings over more complex Reed-Solomon decoders.

    摘要翻译： 一种使用Reed-Solomon解码器对Reed-Solomon码进行解码的系统和方法，该解码器包括共享单个纠错单元的擦除位置选择器，多个校正子形成器和多个Berlekamp-Massey解码器，以及用于选择Berlekamp-Massey解码器输出 作为错误校正单元的输入。 与已知的硬判决和软判决里德 - 所罗门解码器相比，该方法提高了里德 - 所罗门解码器的误码率性能。 Reed-Solomon解码器还通过更复杂的Reed-Solomon解码器提供硬件面积和功耗。

    METHOD FOR USING ERROR CORRECTION CODES WITH N FACTORIAL OR CCI EXTENSION
    86.
    发明申请
    METHOD FOR USING ERROR CORRECTION CODES WITH N FACTORIAL OR CCI EXTENSION 有权
    使用错误修正代码与N工厂或CCI扩展的方法

    公开(公告)号：US20150263823A1

    公开(公告)日：2015-09-17

    申请号：US14214285

    申请日：2014-03-14

    申请人： QUALCOMM Incorporated

    发明人： Shoichiro Sengoku

    IPC分类号： H04L1/00 ,  H03M13/05

    CPC分类号： H04L1/0041 ,  G06F13/40 ,  H03M5/14 ,  H03M13/05 ,  H03M13/31 ,  H04L1/0042 ,  H04L1/0057 ,  H04L25/0272 ,  H04L25/14 ,  H04L2001/0094

    摘要： System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A data payload may be converted to a set of transition numbers, the transition numbers may be converted to a sequence of symbols and an error correction code (ECC) may be calculated from symbols in the sequence of symbols. The ECC corresponds to the data payload and the ECC may be appended to the data payload such that the set of transition numbers includes transition numbers corresponding to the ECC. The sequence of symbols is then transmitted on a plurality of signal wires. Clock information is encoded in the sequence of symbols. The clock information may be encoded by ensuring that each pair of consecutive symbols in the sequence of symbols includes two symbols that produce different signaling states on the plurality of signal wires.

    摘要翻译： 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 可以将数据有效载荷转换成一组转换号码，转换号码可以被转换成符号序列，并且可以从符号序列中的符号计算纠错码（ECC）。 ECC对应于数据有效载荷，并且ECC可以附加到数据有效载荷，使得该组转换号包括对应于ECC的转移号。 然后，在多条信号线上发送符号序列。 时钟信息以符号序列编码。 可以通过确保符号序列中的每对连续符号包括在多条信号线上产生不同信令状态的两个符号来编码时钟信息。

    Systems and methods for iterative data processing using feedback iteration
    87.
    发明授权
    Systems and methods for iterative data processing using feedback iteration 有权
    使用反馈迭代迭代数据处理的系统和方法

    公开(公告)号：US09112539B2

    公开(公告)日：2015-08-18

    申请号：US13654417

    申请日：2012-10-18

    申请人： LSI Corporation

    发明人： Fan Zhang

    IPC分类号： H03M13/00 ,  H03M13/05 ,  H03M13/29 ,  H03M13/37 ,  H03M13/11 ,  H03M13/41

    CPC分类号： H03M13/658 ,  H03M13/1111 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/4138 ,  H03M13/6337 ,  H03M13/6343

    摘要： Systems and methods for data processing. In one case, a data processing system includes a data detector circuit configured to apply a data detection algorithm to a detector input to yield a second detected output, and a data decoder circuit configured to apply a data decoding algorithm to a decoder input to yield a decoded output. The decoder input is derived from an interim data set calculated as a combination of at least a first detected output and the second detected output.

    摘要翻译： 用于数据处理的系统和方法。 在一种情况下，数据处理系统包括：数据检测器电路，被配置为将数据检测算法应用于检测器输入以产生第二检测输出;以及数据解码器电路，被配置为将数据解码算法应用于解码器输入，以产生 解码输出。 解码器输入是从作为至少第一检测输出和第二检测输出的组合计算的中间数据集导出的。

    Data transmission utilizing partitioning and dispersed storage error encoding
    88.
    发明授权
    Data transmission utilizing partitioning and dispersed storage error encoding 有权
    数据传输利用分区和分散存储错误编码

    公开(公告)号：US09112535B2

    公开(公告)日：2015-08-18

    申请号：US13251566

    申请日：2011-10-03

    申请人： S. Christopher Gladwin

    发明人： S. Christopher Gladwin

    IPC分类号： H03M13/00 ,  H03M13/29 ,  H03M13/37 ,  H03M13/43 ,  G11C29/00 ,  G06F17/30 ,  G06F11/10 ,  H03M13/05 ,  H04L12/707

    CPC分类号： H03M13/29 ,  G06F11/1028 ,  G06F11/1076 ,  G06F17/30194 ,  H03M13/05 ,  H03M13/1515 ,  H03M13/373 ,  H03M13/3761 ,  H04L45/24

    摘要： A method begins by a first device obtaining data for transmission to a second device and partitioning the data to produce a plurality of data portions. The method continues with the first device dispersed storage error encoding the plurality of data portions using a plurality of sets of error coding dispersal storage function parameters to produce a plurality of sets of encoded data slices and transmitting the plurality of sets of encoded data slices to the second device via a network. The method continues with a second device receiving at least a decode threshold number of encoded data slices and dispersed storage error decoding the at least a decode threshold number of encoded data slices to produce a decoded data portion for each set of the plurality of sets of encoded data slices. The method continues with the second device recapturing the data from a plurality of decoded data portions.

    摘要翻译： 方法开始于第一设备获取用于传输到第二设备的数据并且划分数据以产生多个数据部分。 该方法继续使用多组错误编码分散存储功能参数来编码多个数据部分的第一设备分散存储错误，以产生多组编码数据片，并将多组编码数据片段发送到 第二设备通过网络。 该方法继续第二设备接收至少解码阈值数量的编码数据片和分散存储错误解码至少解码阈值数量的编码数据片以产生用于编码的多组编码数据片段中的每组的解码数据部分 数据片。 该方法继续，第二设备从多个解码的数据部分重新获取数据。

    Parity data management for a memory architecture
    89.
    发明授权
    Parity data management for a memory architecture 有权
    存储器架构的奇偶校验数据管理

    公开(公告)号：US09106260B2

    公开(公告)日：2015-08-11

    申请号：US13720504

    申请日：2012-12-19

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： James M. O'Connor ,  Vilas K. Sridharan ,  Gabriel H. Loh

    IPC分类号： H03M13/11 ,  G06F11/00 ,  H03M13/53 ,  H03M13/05

    CPC分类号： H03M13/11 ,  G06F11/00 ,  G06F11/1048 ,  H03M13/05

    摘要： A processor system as presented herein includes a processor core, cache memory coupled to the processor core, a memory controller coupled to the cache memory, and a system memory component coupled to the memory controller. The system memory component includes a plurality of independent memory channels configured to store data blocks, wherein the memory controller controls the storing of parity bits in at least one of the plurality of independent memory channels. In some implementations, the system memory is realized as a die-stacked memory component.

    摘要翻译： 如本文所述的处理器系统包括处理器核心，耦合到处理器核心的高速缓存存储器，耦合到高速缓冲存储器的存储器控​​制器以及耦合到存储器控制器的系统存储器组件。 系统存储器组件包括被配置为存储数据块的多个独立存储器通道，其中存储器控制器控制在多个独立存储器通道中的至少一个中存储奇偶校验位。 在一些实现中，系统存储器被实现为管芯堆叠的存储器组件。