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    Energy efficient adaptive data encoding method and circuit
    2.
    发明授权
    Energy efficient adaptive data encoding method and circuit 有权

    公开(公告)号：US10566996B2

    公开(公告)日：2020-02-18

    申请号：US15683231

    申请日：2017-08-22

    申请人： Greg Sadowski ,  John Kalamatianos

    发明人： Greg Sadowski ,  John Kalamatianos

    IPC分类号： H04B1/16 ,  H03M7/30 ,  H04B1/04 ,  H04B3/54

    摘要： Various energy efficient data encoding schemes and computing devices are disclosed. In one aspect, a method of transmitting data from a transmitter to a receiver connected by plural wires is provided. The method includes sending from the transmitter on at least one but not all of the wires a first wave form that has first and second signal transitions. The receiver receives the first waveform and measures a first duration between the first and second signal transitions using a locally generated clock signal not received from the transmitter. The first duration is indicative of a first particular data value.

    Depleted sidewall-poly LDD transistor
    4.
    发明授权
    Depleted sidewall-poly LDD transistor 失效
    耗尽的侧壁多LDD晶体管

    公开(公告)号：US5804856A

    公开(公告)日：1998-09-08

    申请号：US753616

    申请日：1996-11-27

    申请人： Dong-Hyuk Ju

    发明人： Dong-Hyuk Ju

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/6659 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/7836 ,  Y10S438/976

    摘要： The present invention is directed to a metal oxide semiconductor transistor having a fully overlapped lightly doped drain (LDD) structure which offers the advantages of conventional fully overlapped LDD transistors but which significantly reduces the drain-to-gate overlap capacitance associate therewith. To achieve fully overlapped LDD construction and reduced drain-to-gate overlap capacitance, the metal oxide semiconductor transistor of the present invention employs a gate electrode comprising a main gate region formed from heavily doped polysilicon and depleted sidewall polysilicon spacers formed from undoped or depleted polysilicon. In the MOS transistor of the present invention, the lightly doped regions are fully overlapped by the combination of the depleted sidewall polysilicon spacers and the main gate region.

    摘要翻译： 本发明涉及一种具有完全重叠的轻掺杂漏极（LDD）结构的金属氧化物半导体晶体管，其提供常规全重叠LDD晶体管的优点，但是显着降低与其相关联的漏极到栅极重叠电容。 为了实现完全重叠的LDD结构和减少的漏极到栅极重叠电容，本发明的金属氧化物半导体晶体管采用栅电极，其包括由重掺杂多晶硅形成的主栅极区域和由未掺杂或耗尽的多晶硅形成的贫化的侧壁多晶硅间隔物 。 在本发明的MOS晶体管中，轻掺杂区域被耗尽的侧壁多晶硅间隔物和主栅极区域的组合完全重叠。

    Peripheral interface circuit for handling graphics responses in an I/O node of a computer system
    6.
    发明申请
    Peripheral interface circuit for handling graphics responses in an I/O node of a computer system 有权
    用于处理计算机系统的I / O节点中的图形响应的外围接口电路

    公开(公告)号：US20030074493A1

    公开(公告)日：2003-04-17

    申请号：US10093346

    申请日：2002-03-07

    申请人： Advanced Mirco Devices, Inc.

    发明人： Tahsin Askar ,  James R. Magro

    IPC分类号： G06F003/00

    CPC分类号： G06F13/128

    摘要： A peripheral interface circuit for handling graphics responses in an I/O node of a computer system. A peripheral interface circuit includes a buffer circuit coupled to receive packet commands. The buffer circuit includes a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected packet commands that belong to the respective virtual channel. The peripheral interface circuit may determine whether a given one of the received packet commands is a graphics response belonging to a particular respective virtual channel. In response to determining that the given packet command is a graphics response belonging to the particular respective virtual channel, the buffer circuit may cause the given packet command to bypass the plurality of buffers.

    摘要翻译： 一种用于处理计算机系统的I / O节点中的图形响应的外围接口电路。 外围接口电路包括耦合以接收分组命令的缓冲电路。 缓冲电路包括多个缓冲器，每个缓冲器对应于多个虚拟通道的相应虚拟通道，用于存储属于相应虚拟通道的所选择的分组命令。 外围接口电路可以确定所接收的分组命令中的给定的一个是属于特定的相应虚拟信道的图形响应。 响应于确定给定分组命令是属于特定相应虚拟信道的图形响应，缓冲器电路可以使给定分组命令绕过多个缓冲器。

    Method and apparatus for eliminating word line bending by source side implantation
    7.
    发明授权
    Method and apparatus for eliminating word line bending by source side implantation 有权
    通过源侧植入消除字线弯曲的方法和装置

    公开(公告)号：US07029975B1

    公开(公告)日：2006-04-18

    申请号：US10839561

    申请日：2004-05-04

    申请人： Shenqing Fang ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani

    发明人： Shenqing Fang ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/513

    摘要： A method and apparatus for coupling to a source line is disclosed. A semiconductor structure having an array of memory cells arranged in rows and columns is described. The array of memory cells includes a source region that is implanted with n-type dopants isolated between an adjoining pair of the non-intersecting STI regions and isolated from a drain region during the implantation. A source contact is located along a row of drain contacts that are coupled to drain regions of a row of memory cells and the source contact is coupled to the source region for providing electrical coupling with a plurality of source lines. The isolating of the implanted source region from the drain region during the implanting enables coupling of the source contact to the source lines while maintaining the n-type dopants between the STI regions and avoiding lateral diffusion to a bit-line.

    摘要翻译： 公开了一种用于耦合到源极线的方法和装置。 描述了具有排列成行和列的存储单元阵列的半导体结构。 存储单元阵列包括源区域，其注入在相邻的一对不相交的STI区域之间隔离并在植入期间与漏区隔离的n型掺杂剂。 源极触点沿着一排漏极触点排列，其被连接到一行存储器单元的漏极区域，并且源极触点耦合到源极区域以提供与多个源极线的电耦合。 在植入期间将注入的源极区域与漏极区域隔离使得能够将源极接触耦合到源极线，同时保持STI区域之间的n型掺杂剂并且避免横向扩散到位线。

    Total tool control for semiconductor manufacturing
    9.
    发明授权
    Total tool control for semiconductor manufacturing 有权
    半导体制造的刀具总控制

    公开(公告)号：US07292959B1

    公开(公告)日：2007-11-06

    申请号：US11342759

    申请日：2006-01-30

    申请人： Richard J. Markle ,  Thomas J. Sonderman

    发明人： Richard J. Markle ,  Thomas J. Sonderman

    IPC分类号： G06F19/00

    CPC分类号： G05B19/41875 ,  G05B2219/42001 ,  G05B2219/45031 ,  Y02P90/22

    摘要： The present invention provides a method and apparatus for controlling processing tools and related control units. The method includes accessing information indicative of at least one excursion of at least one processing tool detected by a first control unit associated with the at least one processing tool. The method also includes determining at least one action to be taken by at least one second control unit associated with the at least one processing tool based on the information indicative of said at least one excursion.

    摘要翻译： 本发明提供一种用于控制加工工具和相关控制单元的方法和装置。 该方法包括访问指示由与至少一个处理工具相关联的第一控制单元检测到的至少一个处理工具的至少一个偏移的信息。 该方法还包括基于指示所述至少一个偏移的信息来确定由与至少一个处理工具相关联的至少一个第二控制单元采取的至少一个动作。

    Electronic system having a multistage low noise output buffer system
    10.
    发明授权
    Electronic system having a multistage low noise output buffer system 失效
    具有多级低噪声输出缓冲系统的电子系统

    公开(公告)号：US6037810A

    公开(公告)日：2000-03-14

    申请号：US919126

    申请日：1997-08-26

    申请人： Gregory C. Woodward

    发明人： Gregory C. Woodward

    IPC分类号： H03K5/13 ,  H03K19/003 ,  H03K17/687

    CPC分类号： H03K19/00361 ,  H03K5/133

    摘要： In one embodiment, a multistage output buffer supplies current to a load by successively turning ON output buffer circuits which transition from an OFF state to approximately a saturated state during approximately mutually exclusive periods of time. Thus, the aggregate dI/dt of the contributed by the output buffer drivers is primarily associated with a single output buffer driver. Additionally, the respective output driver transition periods are controlled by delay stage impedance to reduce dI/dt. The consecutive activation of the output buffer drivers may be achieved by using respective delay stages to control activation of associated, respective output buffer drivers. Each delay stage receives a delayed output control signal from a previous delay stage, except for the first delay stage which receives a control input signal from a signal source. Each delay stage also delays activation of its own output control signal with delay circuit elements such as relatively HIGH impedance IGFETs. The output control signals from each delay stage relatively slowly charge a gate of the associated, respective output buffer driver to activate the output buffer driver and cause a successive delay stage to begin activating the respective output control signal of the successive delay stage. In this manner, each delay stage and, thus, each associated, respective output buffer driver depends on the previous delay stage output control signal to begin the state transition of the respective output buffer driver. Furthermore, the number of delay stages to be activated is programmable to conserve power and further decrease dI/dt induced noise.

    摘要翻译： 在一个实施例中，多级输出缓冲器通过在大约相互排斥的时间段期间连续地导通从OFF状态转变到大约饱和状态的输出缓冲器电路来向负载提供电流。 因此，由输出缓冲器驱动器贡献的总体dI / dt主要与单个输出缓冲器驱动程序相关联。 此外，相应的输出驱动器转换周期由延迟级阻抗控制以减小dI / dt。 可以通过使用相应的延迟级来控制关联的相应输出缓冲器驱动器的激活来实现输出缓冲器驱动器的连续激活。 除了从信号源接收控制输入信号的第一延迟级之外，每个延迟级接收来自先前延迟级的延迟输出控制信号。 每个延迟阶段还通过诸如相对高阻抗IGFET的延迟电路元件来延迟其自己的输出控制信号的激活。 来自每个延迟级的输出控制信号相对较慢地对相应的相应输出缓冲器驱动器的门充电以激活输出缓冲器驱动器，并且引起连续的延迟级开始激活连续延迟级的相应输出控制信号。 以这种方式，每个延迟级以及因此每个相关联的输出缓冲器驱动器依赖于先前的延迟级输出控制信号来开始各个输出缓冲器驱动器的状态转换。 此外，要激活的延迟级的数量是可编程的，以节省功率并进一步降低dI / dt感应噪声。