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    Non-volatile memory device with concurrent bank operations
    6.
    发明授权
    Non-volatile memory device with concurrent bank operations 有权

    公开(公告)号：US11600323B2

    公开(公告)日：2023-03-07

    申请号：US17246190

    申请日：2021-04-30

    申请人： Mosaid Technologies Incorporated

    发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    IPC分类号： G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/06

    摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

    CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
    8.
    发明申请
    CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 有权

    公开(公告)号：US20230046725A1

    公开(公告)日：2023-02-16

    申请号：US17731408

    申请日：2022-04-28

    申请人： Mosaid Technologies Incorporated

    发明人： Peter B. Gillingham ,  Graham Allan

    IPC分类号： G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/04 ,  G11C14/00

    摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

    Vertical Gate Stacked NAND and Row Decoder for Erase Operation
    9.
    发明申请
    Vertical Gate Stacked NAND and Row Decoder for Erase Operation 有权
    垂直门堆叠NAND和行解码器，用于擦除操作

    公开(公告)号：US20150092494A1

    公开(公告)日：2015-04-02

    申请号：US14044449

    申请日：2013-10-02

    申请人： Mosaid Technologies Incorporated

    发明人： Hyoung Seub Rhie

    IPC分类号： G11C16/16

    CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/14

    摘要： A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array.

    摘要翻译： 三维集成电路非易失性存储器阵列包括具有多个垂直栅极NAND存储器单元串的存储器阵列，该多个垂直栅极NAND存储器单元串形成在共享一组公共字线的衬底上的不同垂直层中，其中形成了不同的NAND存储器单元串组 在源线结构和位线结构的专用配对之间形成单独的可擦除块，其通过向擦除块擦除块的源极线结构施加擦除电压来寻址和擦除，同时向阵列中的其它源极线结构施加接地电压 以及对阵列中的位线结构的高通电压。

    METHOD AND SYSTEM FOR PROGRAMMING NON-VOLATILE MEMORY WITH JUNCTIONLESS CELLS
    10.
    发明申请
    METHOD AND SYSTEM FOR PROGRAMMING NON-VOLATILE MEMORY WITH JUNCTIONLESS CELLS 有权
    使用无连接电池编程非易失性存储器的方法和系统

    公开(公告)号：US20140133238A1

    公开(公告)日：2014-05-15

    申请号：US13832785

    申请日：2013-03-15

    申请人： MOSAID TECHNOLOGIES INCORPORATED

    发明人： Hyoung Seub Rhie

    IPC分类号： G11C16/10

    CPC分类号： G11C16/10 ,  G11C16/0483

    摘要： A non-volatile memory system that has junctionless transistors is provided that uses suppression of the formation of an inversion-layer source and drain in the junctionless transistors to cause a discontinuous channel in at least one string. The system may include NAND flash memory cells composed of junctionless transistors, and has a set of wordlines. During program operation, a selected wordline of the set of wordlines is biased at a program voltage, and wordline voltage low enough to suppress the formation of source/drains is applied on at least one word line on a source side of the selected wordline such that a channel isolation occurs thereby causing the discontinuous channel in the at least string.

    摘要翻译： 提供了具有无连接晶体管的非易失性存储器系统，其使用抑制在无连接晶体管中形成反型层源极和漏极以在至少一个串中引起不连续通道。 该系统可以包括由无连接晶体管组成的NAND闪存单元，并且具有一组字线。 在编程操作期间，字母集合中的选定字线被偏置在编程电压上，并且低于足以抑制源极/漏极形成的字线电压被施加在所选字线的源极侧的至少一条字线上，使得 发生通道隔离，从而导致至少串中的不连续通道。