公开(公告)号：US6136138A

公开(公告)日：2000-10-24

申请号：US149037

申请日：1998-09-08

申请人： Kouki Yagisawa

发明人： Kouki Yagisawa

IPC分类号： H01L21/304 ,  B24B37/10 ,  H01L21/3105 ,  B24B5/00 ,  B24B29/00 ,  C03C15/00 ,  H01L21/302 ,  H01L21/463

CPC分类号： B24B37/105 ,  H01L21/31053

摘要： The invention involves technology related to chemical mechanical polishing using a chemical mechanical polishing apparatus having a wafer carrier for holding a semiconductor wafer, a polishing platen which is able to be rotated and which is positioned facing the surface of the wafer carrier on which the wafer is held, and a circular polishing cloth mounted on the polishing platen for polishing the semiconductor wafer, the polishing cloth having a smaller diameter than the diameter of the semiconductor wafer, and the polishing platen being movable horizontally across the surface of the semiconductor wafer. While rotating the semiconductor wafer held on the wafer carrier, the polishing platen is moved horizontally across the surface of the semiconductor wafer so that the displacement velocity of the polishing platen is slower at a central portion of the semiconductor wafer than at an outer portion, and the surface of the semiconductor wafer is polished with the polishing cloth. As a result, polishing uniformity is improved.

摘要翻译： 本发明涉及使用具有用于保持半导体晶片的晶片载体的化学机械抛光装置的化学机械抛光技术，能够旋转的抛光平台，其面向晶片载体的表面，晶片载体 以及安装在研磨台板上用于抛光半导体晶片的圆形抛光布，抛光布的直径小于半导体晶片的直径，并且抛光台板可横向于半导体晶片的表面水平移动。 在旋转保持在晶片载体上的半导体晶片的同时，抛光台板横过半导体晶片的表面水平移动，使得抛光压板的位移速度在半导体晶片的中心部分比在外部部分更慢， 用抛光布抛光半导体晶片的表面。 结果，提高了抛光均匀性。

公开(公告)号：US6118173A

公开(公告)日：2000-09-12

申请号：US969770

申请日：1997-11-13

申请人： Yoshiaki Emoto

发明人： Yoshiaki Emoto

IPC分类号： H01L23/495

CPC分类号： H01L24/06 ,  H01L23/49551 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082

摘要： A semiconductor device of this invention includes a semiconductor chip on which a device is formed, inner leads reaching the periphery of the semiconductor chip, and bonding wires for electrically connecting the semiconductor chip and the inner leads. The semiconductor chip is fixed on a die pad portion, and a chip fixing inner lead is integrated with the die pad portion. To simplify the bonding wire connection process and improve the reliability, the chip fixing inner lead has a step portion so that the die pad portion is formed at a lower position than the inner leads. The step portion is formed so as to be offset from a line of the end portions of the inner leads in the opposite direction of the semiconductor chip, so an arbitrary bonding wire can be kept apart from the step portion. According to this invention, a semiconductor device which can properly prevent contact between the step portion and the bonding wire to improve the reliability, and a lead frame applicable to this semiconductor device can be provided.

摘要翻译： 本发明的半导体器件包括其上形成有器件的半导体芯片，到达半导体芯片周围的内部引线，以及用于电连接半导体芯片和内部引线的接合线。 半导体芯片固定在芯片焊盘部分上，芯片固定内引线与芯片焊盘部分集成。 为了简化接合线连接处理并提高可靠性，芯片固定内引线具有阶梯部，使得芯片焊盘部形成在比内引线更低的位置。 台阶部形成为与半导体芯片的相反方向的内部引线的端部的线偏移，因此可以使任意的接合线与台阶部分分离。 根据本发明，可以提供一种可以适当地防止台阶部分和接合线之间的接触以提高可靠性的半导体器件，以及可应用于该半导体器件的引线框架。

公开(公告)号：US06107148A

公开(公告)日：2000-08-22

申请号：US178510

申请日：1998-10-26

申请人： Masushi Taki

发明人： Masushi Taki

IPC分类号： H01L21/266 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/266

摘要： A method for fabricating a semiconductor device having LDD structure. The method includes: a first step for forming an electrically insulating layer on an active area defined on a surface of a semiconductor substrate; a second step for forming a conductive layer on said insulating layer; a third step for forming a patterned photoresist layer of a downward tapered shape on said conductive layer; a fourth step for forming a gate electrode by patterning said conductive layer using a mask provided by bottom portions of said patterned photoresist layer; a fifth step for forming heavilyly doped regions at both sides of said gate electrode by introducing ions using a mask provided by top portions of said patterned photoresist layer; a sixth step for removing said patterned photoresist layer; and a seventh step for forming lightly doped regions at both sides of said gate electrode by introducing ions using a mask provided by said gate electrode.

摘要翻译： 一种制造具有LDD结构的半导体器件的方法。 该方法包括：第一步骤，用于在限定在半导体衬底的表面上的有源区上形成电绝缘层; 在所述绝缘层上形成导电层的第二步骤; 在所述导电层上形成向下锥形的图案化光致抗蚀剂层的第三步骤; 用于通过使用由所述图案化光致抗蚀剂层的底部提供的掩模图案化所述导电层来形成栅电极的第四步骤; 用于通过使用由所述图案化光致抗蚀剂层的顶部提供的掩模引入离子在所述栅电极的两侧形成重掺杂区的第五步骤; 用于去除所述图案化光致抗蚀剂层的第六步骤; 以及通过使用由所述栅电极提供的掩模引入离子在所述栅电极的两侧形成轻掺杂区的第七步骤。

公开(公告)号：US6100598A

公开(公告)日：2000-08-08

申请号：US34405

申请日：1998-03-04

申请人： Kenji Kanesaka

发明人： Kenji Kanesaka

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/28

CPC分类号： H01L21/565 ,  H01L23/3107 ,  H01L2224/05553 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041

摘要： In a semiconductor device having a resin-encapsulated structure, the width of an upper-mold portion of a package in a direction parallel to inner leads is made smaller than that of a lower-mold portion of the package so that the upper-mold portion cannot extend further towards outer leads than the lower-mold portion. Therefore, the amount of the positional deviation between an actual package region and a prospective package region is small and tiebars can be arranged close to the prospective package region in a lead frame. Since a fixed distance is ensured between the tiebars and the actual package region after molding, damage to the package is prevented during tiebar cutting. Since the amount of extension of any resin burr is small, a deflashing step is omitted.

摘要翻译： 在具有树脂封装结构的半导体器件中，包装的与内引线平行的方向的上模部分的宽度小于封装的下模部分的宽度，使得上模部分 不能比下模具部分进一步向外引线延伸。 因此，实际封装区域和预期封装区域之间的位置偏差量很小，并且可以将引线架布置成靠近引线框架中的预期封装区域。 由于在成型后在连杆和实际的包装区域之间确保了固定的距离，所以在拉杆切割期间防止了包装的损坏。 由于任何树脂毛刺的伸长量都较小，所以省略了除屑步骤。

公开(公告)号：US6066535A

公开(公告)日：2000-05-23

申请号：US368799

申请日：1999-08-05

申请人： Ichiro Murai

发明人： Ichiro Murai

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L21/28211 ,  H01L21/28105 ,  H01L21/28114 ,  H01L21/28185 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66575 ,  H01L21/26586

摘要： A gate electrode comprises a conductive gate electrode body and gate side walls. The channel region beneath the gate electrode has an NUDC structure having a p.sup.- impurity region and p.sup.+ impurity regions. The p.sup.- impurity region is formed before the gate electrode body. After the formation of the gate electrode body, the p.sup.+ impurity regions are formed by ion implantation before the gate side walls. The ion implantation is carried out perpendicular to the substrate so that the implanted ions will not reach further around the center of the channel region. Of the gate oxide films over the channel region, the thickness of the gate oxide films at both ends of the channel region is thinner than that of the gate oxide film in the middle of the channel length so as to suppress lowering of the current drivability.

摘要翻译： 栅电极包括导电栅电极体和栅极侧壁。 栅电极下方的沟道区具有具有p杂质区和p +杂质区的NUDC结构。 p型杂质区域形成在栅电极本体之前。 在形成栅极电极体之后，在栅极侧壁之前通过离子注入形成p +杂质区域。 离子注入是垂直于衬底进行的，因此注入的离子将不会进一步靠近沟道区的中心。 在沟道区域上的栅极氧化膜中，沟道区两端的栅极氧化膜的厚度比沟道长度中间的栅极氧化膜的厚度薄，以抑制电流驱动性的降低。

公开(公告)号：US6008688A

公开(公告)日：1999-12-28

申请号：US50309

申请日：1998-03-30

申请人： Jon Allan Faue

发明人： Jon Allan Faue

IPC分类号： H03K3/356 ,  H03K17/22 ,  H03K17/16

CPC分类号： H03K3/356147 ,  H03K17/223

摘要： A latch-up protector, and an associated method, for an electronic circuit powered by both a fixed power supply and a pumped power supply. Operation of the latch-up protector prevents the occurrence of latch-up of the circuit during powering-up of the circuit. During powering-up of the electronic circuit, the latch-up protector prevents the application of an input signal to the electronic circuit which might instigate the occurrence of latch-up until the pumped power supply reaches a selected voltage level.

摘要翻译： 一种用于由固定电源和抽吸电源供电的电子电路的闭锁保护器和相关联的方法。 闩锁保护器的操作防止在电路通电期间电路闭锁的发生。 在电子电路加电期间，闩锁保护器防止向电子电路施加输入信号，这可能引起闩锁的发生，直到泵送的电源达到选定的电压电平。

公开(公告)号：US6000900A

公开(公告)日：1999-12-14

申请号：US791666

申请日：1997-01-30

申请人： Teruo Isogai

发明人： Teruo Isogai

IPC分类号： B65D85/38 ,  B65G49/07 ,  H01L21/00 ,  H01L21/673 ,  H01L21/677 ,  B65H5/00

CPC分类号： H01L21/6773 ,  H01L21/67276 ,  Y10S414/14

摘要： A wafer cassette conveying system is capable of reducing a communication amount between a conveying device and a control device, further shortening the time period required for a movement of the conveying device. A control device 15, when receiving both of a lot carrying-in request signal outputted from a first treating device 11 and an empty cassette carrying-out request signal outputted from a second treating device 12, outputs a lot carrying-in command signal. A conveying device 20, when receiving this lot carrying-in command signal, conveys an actual cassette of the first treating device 11 to the second treating device 12 and also conveys an empty cassette of the second treating device 12 to an empty cassette space 14.

摘要翻译： 晶片盒输送系统能够减少输送装置和控制装置之间的通信量，进一步缩短输送装置运动所需的时间。 控制装置15在接收到从第一处理装置11输出的批次输入请求信号和从第二处理装置12输出的空盒执行请求信号两者时输出批输入命令信号。 输送装置20在接收到该批次输入命令信号时，将第一处理装置11的实际盒传送到第二处理装置12，并将第二处理装置12的空盒输送到空盒体空间14。

公开(公告)号：US5900021A

公开(公告)日：1999-05-04

申请号：US833105

申请日：1997-04-04

申请人： John William Tiede ,  Jon Allan Faue

发明人： John William Tiede ,  Jon Allan Faue

IPC分类号： G11C7/10 ,  H03K19/173 ,  G06F12/00 ,  G11C7/00

CPC分类号： H03K19/173 ,  G11C7/1045

摘要： A configurable input device for an integrated circuit having a plurality of input pads, the input device including a plurality of buffers, where each buffer is associated with one of the input pads. Each buffer receives a mode select signal and the buffer is responsive to the mode select signal to place the buffer in an enabled mode or a disabled mode. A receiver portion within each buffer is coupled to the associated input pad. The receiver portion pulls the associated input pad to a preselected logic state while the buffer is in the disabled mode. An output driver within each buffer generates an output signal responsive to a signal on the associated input pad while the buffer is in the enable mode and provides a high impedance while the buffer is in the disabled mode. An output node is coupled to the output drivers of the plurality of buffers.

摘要翻译： 一种用于具有多个输入焊盘的集成电路的可配置输入设备，所述输入设备包括多个缓冲器，其中每个缓冲器与所述输入焊盘中的一个相关联。 每个缓冲器接收模式选择信号，并且缓冲器响应于模式选择信号以将缓冲器置于启用模式或禁用模式。 每个缓冲器内的接收器部分耦合到相关联的输入焊盘。 当缓冲器处于禁用模式时，接收器部分将相关联的输入焊盘拉至预选逻辑状态。 每个缓冲器中的输出驱动器在缓冲器处于使能模式时响应于相关输入焊盘上的信号产生输出信号，并且在缓冲器处于禁用模式时提供高阻抗。 输出节点耦合到多个缓冲器的输出驱动器。

公开(公告)号：US5760441A

公开(公告)日：1998-06-02

申请号：US738419

申请日：1996-10-25

申请人： Eiichi Iwanami

发明人： Eiichi Iwanami

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L27/146 ,  H01L31/0232 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/14643 ,  H01L27/0251 ,  H01L27/0266 ,  H01L31/0232

摘要： A p-type high concentration doped region is formed in a p-type semiconductor substrate between a n-type doped region as part of an input protection circuit and another n-type doped region as part of internal circuitry. A plate is divided into two over the high concentration doped region. The high concentration doped region suppresses generation of a parasitic MOS transistor with the plate for a gate, one of the n-type doped regions for a source, and the other for a drain.

摘要翻译： 作为输入保护电路的一部分的n型掺杂区域和作为内部电路的一部分的另一个n型掺杂区域，在p型半导体衬底中形成p型高浓度掺杂区域。 在高浓度掺杂区域上将板分成两部分。 高浓度掺杂区域抑制寄生MOS晶体管的产生，栅极用栅极，用于源极的n型掺杂区域中的一个，漏极的另一个。

公开(公告)号：US5754464A

公开(公告)日：1998-05-19

申请号：US766505

申请日：1996-12-13

申请人： Yugo Tomioka

发明人： Yugo Tomioka

IPC分类号： H01L21/76 ,  G11C17/12 ,  H01L21/8246 ,  H01L27/112 ,  G11C17/10

CPC分类号： G11C17/12 ,  H01L27/112

摘要： A mask ROM with increased memory capacity is disclosed. Besides MOS transistors each comprising a memory cell, MOS field shield transistors for device isolation, originally provided for electrically isolating the memory cell transistors, are also used as additional memory cells in addition to providing their isolating function. To write data in one of the field shield transistor, the threshold voltage of the field shield transistor is lowered, compared to field shield transistors in other regions. This is done by ion implantation of an n-type impurity into a p-type silicon substrate in a region beneath a gate electrode of the field shield transistor (a channel region). Data is read by judging on/off of the transistors when an intermediate voltage, between a high threshold voltage and a low threshold voltage is applied to a field shield line.

摘要翻译： 公开了具有增加的存储容量的掩模ROM。 除了各自包括存储单元的MOS晶体管之外，还提供用于电隔离存储单元晶体管的用于器件隔离的MOS场屏蔽晶体管，除了提供它们的隔离功能之外还用作附加存储器单元。 为了在场屏蔽晶体管之一中写入数据，与其他区域中的场屏蔽晶体管相比，场屏蔽晶体管的阈值电压降低。 这通过在场屏蔽晶体管（沟道区域）的栅电极下方的区域中将n型杂质离子注入到p型硅衬底中来完成。 当将高阈值电压和低阈值电压之间的中间电压施加到场屏蔽线时，通过判断晶体管的开/关来读取数据。