公开(公告)号：US20210375672A1

公开(公告)日：2021-12-02

申请号：US17112119

申请日：2020-12-04

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Hao Chun Liu ,  Po-Hao Tsai ,  Chih-Hsien Lin ,  Ching-Wen Hsiao

IPC分类号： H01L21/768 ,  H01L21/48 ,  H01L23/532 ,  H01L23/00

摘要： A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.

公开(公告)号：US10541162B2

公开(公告)日：2020-01-21

申请号：US15882272

申请日：2018-01-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chao-Hsiang Liu

IPC分类号： G06F7/00 ,  H01L21/67 ,  G01B11/00 ,  B25J9/16 ,  B25J11/00 ,  H01L21/687 ,  H01L21/68 ,  H01L21/673 ,  H01L21/677

摘要： In an embodiment, a system includes: a wafer pod defining a cavity configured to store a wafer at a wafer position; calibration sensors within the cavity, each calibration sensor configured to produce calibration data indicating that the wafer is at a respective part of the cavity; and a processor configured to determine whether the wafer is positioned at the wafer position within the cavity based on the calibration data.

公开(公告)号：US10276445B2

公开(公告)日：2019-04-30

申请号：US15692769

申请日：2017-08-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Sheng Fan ,  Chun-Yen Lin ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

摘要： A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.

公开(公告)号：US08134163B2

公开(公告)日：2012-03-13

申请号：US12247895

申请日：2008-10-08

申请人： Chen-Hua Yu ,  Hung-Ta Lin ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu

发明人： Chen-Hua Yu ,  Hung-Ta Lin ,  Wen-Chih Chiou ,  Ding-Yuan Chen ,  Chia-Lin Yu

IPC分类号： H01L33/08

CPC分类号： H01L33/48 ,  H01L33/20 ,  H01L33/24

摘要： A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.

摘要翻译： 提供了一种形成在凹面纹理基板上的发光二极管（LED）的半导体器件。 对衬底进行图案化和蚀刻以形成凹陷。 沿着凹部的底部形成分离层。 沿着侧壁和任选地沿着相邻凹部之间的基板的表面形成LED结构。 在这些实施例中，与平面表面相比，LED结构的表面积增加。 在另一个实施例中，LED结构形成在凹部内，使得底部接触层与凹部的拓扑不一致。 在这些实施例中，硅衬底中的凹陷导致底接触层中的立方结构，例如具有非极性特性并且表现出更高外部量子效率的n-GaN层。

公开(公告)号：US20220238697A1

公开(公告)日：2022-07-28

申请号：US17333592

申请日：2021-05-28

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Szu-Ying Chen

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L29/417

摘要： A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

公开(公告)号：US20230131688A1

公开(公告)日：2023-04-27

申请号：US17832979

申请日：2022-06-06

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Da-Yuan Lee ,  Weng Chang

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/306

摘要： Embodiments include a nanoFET device and method for forming the same, the nanoFET having channel regions which have been thinned during a gate replacement process to remove etching residue. In some embodiments, the channel regions become dog bone shaped. In some embodiments, the ends of the channel regions have vertical protrusions or horns resulting from a previous trimming process which is performed prior to depositing sidewall spacers.

公开(公告)号：US20220367610A1

公开(公告)日：2022-11-17

申请号：US17875026

申请日：2022-07-27

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Chen-Yin HSU ,  Chun Li WU ,  Ching-Hung KAO

IPC分类号： H01L49/02

摘要： The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.

公开(公告)号：US20220302105A1

公开(公告)日：2022-09-22

申请号：US17836899

申请日：2022-06-09

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Ming-Fu Tsai ,  Tzu-Heng Chang ,  Yu-Ti Su ,  Kai-Ping Huang

IPC分类号： H01L27/02

摘要： An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

公开(公告)号：US10170488B1

公开(公告)日：2019-01-01

申请号：US15865454

申请日：2018-01-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Bo Shu ,  Tsung-Yu Yang ,  Chung-Jen Huang

IPC分类号： H01L21/00 ,  H01L27/11517 ,  H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L21/762

摘要： A semiconductor device includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, a first floating gate structure, a second floating gate structure, a first word line, a common source, a second word line, a first spacer and a second spacer. The first floating gate structure and the second floating gate structure are recessed in the substrate at two opposite sides of the erase gate structure. The first word line and the second word line are respectively adjacent to the first floating gate structure and the second floating gate structure. The common source is disposed in the substrate under the erase gate structure. The first spacer and the second spacer are respectively disposed between the first floating gate structure and the first word line and between the second floating gate structure and the second word line.

公开(公告)号：US07226860B2

公开(公告)日：2007-06-05

申请号：US10833154

申请日：2004-04-28

申请人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

发明人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

IPC分类号： H01L21/44

CPC分类号： H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.