公开(公告)号：US20230162979A1

公开(公告)日：2023-05-25

申请号：US17562045

申请日：2021-12-27

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Nuo-Wei Luo

IPC分类号： H01L21/027 ,  G03F7/16

CPC分类号： H01L21/027 ,  G03F7/168

摘要： A wafer processing method includes: providing a wafer, wherein the wafer has a first position and a second position, and the first position faces the second position in a reference direction; coating a photoresist liquid on the wafer; and performing a heating process to heat the wafer coated with the photoresist liquid to form a photoresist layer on the wafer, wherein during the heating process, a temperature of the wafer gradually increases in the reference direction, so that a thickness of the photoresist layer gradually decreases in the reference direction.

公开(公告)号：US20230145660A1

公开(公告)日：2023-05-11

申请号：US17539222

申请日：2021-12-01

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Hau-Yuan Huang ,  Chia-Chen Tsai ,  Jia-Bin Yeh ,  Shou-Wei Hsieh

IPC分类号： H01L27/146

CPC分类号： H01L27/14612 ,  H01L27/14689

摘要： An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.

公开(公告)号：US20220108946A1

公开(公告)日：2022-04-07

申请号：US17064609

申请日：2020-10-07

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Chien-Ming Lai ,  Zhi-Rui Sheng ,  Hui-Ling Chen

IPC分类号： H01L23/522 ,  H01L49/02

摘要： A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.

公开(公告)号：US10199232B2

公开(公告)日：2019-02-05

申请号：US13033696

申请日：2011-02-24

申请人： Shin-Chi Chen ,  Jiunn-Hsiung Liao ,  Yu-Tsung Lai

发明人： Shin-Chi Chen ,  Jiunn-Hsiung Liao ,  Yu-Tsung Lai

IPC分类号： H01L29/49 ,  H01L21/311 ,  H01L21/768

摘要： Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.

公开(公告)号：US10121869B2

公开(公告)日：2018-11-06

申请号：US15832733

申请日：2017-12-05

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Weichang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Wei Ta

IPC分类号： H01L27/092 ,  H01L29/423 ,  H01L29/792 ,  H01L29/06 ,  H01L27/11568 ,  H01L29/66

摘要： A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.

公开(公告)号：US09916978B2

公开(公告)日：2018-03-13

申请号：US15170958

申请日：2016-06-02

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chao-Hung Lin

IPC分类号： H01L21/3065 ,  H01L21/02 ,  H01L29/66 ,  H01L21/308 ,  H01L21/306

CPC分类号： H01L21/02636 ,  H01L21/02532 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/6656 ,  H01L29/66818

摘要： The invention provides a method for fabricating a fin field effect transistor (FinFET), comprising: providing a substrate having a logic region and a large region; forming a plurality of fin structures in the logic region by removing a portion of the substrate in the logic region; forming an oxide layer on the substrate filling in-between the fin structures in the logic region; forming an first epitaxial structure in the large region by removing a portion of the substrate in the large region; exposing a portion of the fin structures and a portion of the epitaxial structure by removing a portion of the oxide layer; and forming a gate electrode on portions of the fin structures.

公开(公告)号：US09780193B2

公开(公告)日：2017-10-03

申请号：US14924479

申请日：2015-10-27

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Chia-Lin Lu ,  Yu-Cheng Tung ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

摘要： A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.

公开(公告)号：US20170271153A1

公开(公告)日：2017-09-21

申请号：US15071124

申请日：2016-03-15

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： TSUNG-HSUN TSAI

IPC分类号： H01L21/02 ,  H01L29/66

CPC分类号： H01L21/02661 ,  H01L21/02658 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66636

摘要： The invention provides a method of epitaxial structure formation in a semiconductor, comprising: providing a substrate; performing a dry etch to form a first recess; after performing the dry etch, performing a SPM cleaning process on the substrate by using a nozzle spraying SPM solution with an angle greater than zero and less than 45 degrees relative to the substrate; after performing the SPM cleaning process, performing a wet etch to form a second recess; after performing the wet etch, performing a pre-epi cleaning process; and growing an epitaxial structure in the second recess.

公开(公告)号：US09678530B2

公开(公告)日：2017-06-13

申请号：US14819444

申请日：2015-08-06

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Chien-Hung Chen

IPC分类号： G06F17/50 ,  H03K19/177 ,  G06F1/10 ,  H01L23/522

CPC分类号： G06F1/10 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/62 ,  G06F2217/84 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/17736 ,  H03K19/1774 ,  H01L2924/00

摘要： An clock skew adjusting structure is provided. The clock skew adjusting structure includes a substrate, a wiring structure, a first active component and a second active component. The wiring structure includes at least a wiring layer and at least a via, the via is configured for different wiring layers to be electrically connected with each other. The first active component is formed on the substrate and configured for delivering a clock signal to the wiring structure. The second active component is formed on the substrate and electrically connected to the first active component through the wiring structure thus forming a timing path. The second active component receives the clock signal through the timing path.

公开(公告)号：US09478457B2

公开(公告)日：2016-10-25

申请号：US14957585

申请日：2015-12-02

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Ming-Shing Chen ,  Yu-Ting Wang ,  Ming-Hui Chang

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/76224

摘要： Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.

摘要翻译： 半导体器件中的浅沟槽隔离结构及其制造方法。 该方法包括以下步骤。 衬底上设置衬垫氧化物层和其上的第一图案化的光刻胶层。 在对应于第一图案化光致抗蚀剂层的基板中形成第一沟槽。 第一介电层沉积在第一沟槽和衬底上。 提供第二图案化光致抗蚀剂层以在第一电介质层中形成开口，并且在衬底中形成对应于第二图案化光致抗蚀剂层的第二沟槽。 沉积第二电介质层以覆盖衬底中的第一沟槽和第二沟槽以及衬底上的第一介电层。 通过化学机械抛光除去第二介电层，直到暴露第一​​介电层。 选择性地去除衬底上的第一介电层。