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    Structures for word line multiplexing in three-dimensional memory arrays
    1.
    发明授权
    Structures for word line multiplexing in three-dimensional memory arrays 有权

    公开(公告)号：US12131794B2

    公开(公告)日：2024-10-29

    申请号：US17893681

    申请日：2022-08-23

    申请人： Micron Technology, Inc.

    发明人： Fatma Arzum Simsek-Ege ,  Mingdong Cui ,  Richard E. Fackenthal

    IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  H10B12/00

    CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  H10B12/488

    摘要： Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include one or more gate material portions operable to modulate a conductivity between respective first and second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material portions may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.

    Detecting data bus drive faults
    2.
    发明授权
    Detecting data bus drive faults 有权

    公开(公告)号：US12130702B2

    公开(公告)日：2024-10-29

    申请号：US17880220

    申请日：2022-08-03

    申请人： Micron Technology, Inc.

    发明人： Melissa I. Uribe

    IPC分类号： G06F11/10 ,  G06F11/00

    CPC分类号： G06F11/1048 ,  G06F11/1076

    摘要： Methods, systems, and devices for memory operations are described. A pin associated with communicating error correction information may be biased, via a first circuit, to a first voltage level by a first voltage source that is coupled with the pin when the pin is in an idle state. Also, a set of data pins may be biased, via a second circuit, to a second voltage level by a second voltage source when the set of data pins is in the idle state. When a memory device misses a command transmitted from a host device, the voltage levels of the pin and set of data pins may remain at the respective voltage levels throughout a period during which the host device executes an operation associated with the missed command, indicating to the host device that data communicated by a corresponding data signal is invalid.

    Channel state feedback using demodulation reference signals
    5.
    发明授权
    Channel state feedback using demodulation reference signals 有权

    公开(公告)号：US12126466B2

    公开(公告)日：2024-10-22

    申请号：US17690315

    申请日：2022-03-09

    申请人： QUALCOMM Incorporated

    发明人： Ronen Shaked ,  Aviv Regev

    IPC分类号： H04L25/02 ,  H04B7/06 ,  H04L5/00

    CPC分类号： H04L25/0228 ,  H04B7/0626 ,  H04L5/0048

    摘要： Methods, systems, and devices for wireless communications are described. A user equipment (UE) may monitor for a demodulation reference signal (DMRS) according to a default precoder, where the DMRS is associated with channel state feedback (CSF) information. The UE may perform a channel estimation based on the DMRS, and transmit an uplink message indicating one or more candidate precoders, where the one or more candidate precoders are selected based on the channel estimation. The UE may receive a downlink message indicating a precoder of the one or more candidate precoders based on transmitting the uplink message. The UE may then communicate with a network entity in accordance with the indicated precoder based on receiving the downlink message.

    Techniques for data transfer operations
    7.
    发明授权
    Techniques for data transfer operations 有权

    公开(公告)号：US12124723B2

    公开(公告)日：2024-10-22

    申请号：US17729837

    申请日：2022-04-26

    申请人： Micron Technology, Inc.

    发明人： Jotiba Koparde

    IPC分类号： G06F12/00 ,  G06F3/06

    CPC分类号： G06F3/0647 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673

    摘要： Methods, systems, and devices for techniques for data transfer operations are described. A memory system may select a source set of memory cells and a destination set of memory cells using one or more counters corresponding to access operations for the source and the destination. For example, as part of a data transfer operation, the memory system may prioritize transferring data from a block with a lower quantity of read operations to a block with a lower quantity of access operations. In some cases, the memory system may prioritize transferring data from a page with a lower quantity of read operations to a page with a slower read duration.

    Data organization for logical to physical table compression
    8.
    发明授权
    Data organization for logical to physical table compression 有权

    公开(公告)号：US12124365B2

    公开(公告)日：2024-10-22

    申请号：US17420210

    申请日：2021-05-05

    申请人： Micron Technology, Inc.

    发明人： Yanhua Bi

    IPC分类号： G06F12/02 ,  G06F13/16

    CPC分类号： G06F12/0246 ,  G06F13/1668 ,  G06F2212/401 ,  G06F2212/7201

    摘要： Methods, systems, and devices for data organization for logical to physical table compression are described. The memory system may identify a region that includes one or more logical addresses associated with discontinuous corresponding physical addresses. The memory system may include a plurality of regions of logical addresses and a plurality of memory cells arranged according to a plurality of physical addresses. The memory system may determine a period of inactivity of access operations on the plurality of memory cells and rearrange, during the period of inactivity, information stored within the discontinuous corresponding physical addresses to be within continuous physical addresses of the plurality of physical addresses.

    Multiple transistor architecture for three-dimensional memory arrays
    10.
    发明授权
    Multiple transistor architecture for three-dimensional memory arrays 有权

    公开(公告)号：US12119056B2

    公开(公告)日：2024-10-15

    申请号：US17701463

    申请日：2022-03-22

    申请人： Micron Technology, Inc.

    发明人： Ferdinando Bedeschi

    IPC分类号： G11C13/00 ,  G11C16/04 ,  H10B43/20

    CPC分类号： G11C13/0026 ,  G11C13/0004 ,  G11C16/0483 ,  H10B43/20 ,  G11C2213/71

    摘要： Methods, systems, and devices for multiple transistor architecture for three-dimensional memory arrays are described. A memory device may include conductive pillars coupled with an access line using two transistors positioned between the conductive pillar and the access line. As part of an access operation for a memory cell coupled with the conductive pillar, the memory device may be configured to bias the access line to a first voltage and activate the two transistors using a second voltage to couple the conductive pillar with the access line. Additionally, the memory device may be configured to bias a gate of a first transistor and a gate of a second transistor coupling an unselected conductive pillar with the access line to a third and fourth voltage, respectively, which may deactivate at least one of the first or second transistor during the access operation and isolate the unselected conductive pillar from the access line.