公开(公告)号：US06795009B2

公开(公告)日：2004-09-21

申请号：US10237903

申请日：2002-09-09

申请人： Thomas P. Duffy ,  Malay Trivedi ,  Kevin Mori

发明人： Thomas P. Duffy ,  Malay Trivedi ,  Kevin Mori

IPC分类号： H03M112

CPC分类号： H02M3/1584 ,  H02M3/157

摘要： Currents flowing in the various channels within a voltage regulator module (VRM) are suitably converted to digital equivalents that can be processed to control each module in a modular power supply. Functions that may be digitally implemented include current balancing between channels, current sharing between various modules in a power supply, and/or the like. By monitoring the current provided on each channel within a module, for example, a controller can determine an average current for the channels, which in turn can be used to identify and compensate for over- or under-production in any particular channel. Active voltage positioning techniques and overload protection may also be implemented using digital techniques.

摘要翻译： 在电压调节器模块（VRM）内的各种通道中流动的电流适当地转换为可被处理以控制模块化电源中的每个模块的数字等效电路。 可以数字实现的功能包括通道之间的电流平衡，电源中的各个模块之间的电流共享等等。 通过监视在模块内的每个通道上提供的电流，例如，控制器可以确定通道的平均电流，这又可以用于识别和补偿任何特定通道中的过度或不足的产生。 有源电压定位技术和过载保护也可以使用数字技术实现。

公开(公告)号：US5384690A

公开(公告)日：1995-01-24

申请号：US97544

申请日：1993-07-27

申请人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

发明人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

IPC分类号： H01R4/26 ,  H01R4/58 ,  H01R12/61 ,  H01R13/66 ,  H05K1/00 ,  H05K1/03 ,  H05K1/14 ,  H05K3/00 ,  H05K3/32 ,  H05K3/46 ,  H01R23/68

CPC分类号： H05K3/4635 ,  H01R12/613 ,  H01R13/665 ,  H05K3/462 ,  H01R4/26 ,  H01R4/58 ,  H05K1/0373 ,  H05K1/0393 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10159 ,  H05K3/328 ,  H05K3/4623 ,  H05K3/4641 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49179 ,  Y10T428/24917

摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.

摘要翻译： 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。 各个子组件的层压是通过与要层压的区域中的子组件之间的全氟化碳聚合物化学相容（可粘合）化学相容的低熔点粘合剂，以及任选的与化学不相容的高熔点掩模 可粘合到）在不想层压的区域中的子组件之间的全氟化碳聚合物。 加热组件叠层以选择性地在要层压的区域中进行粘合和层压，同时避免在不想层压的区域中层压。

公开(公告)号：US5055151A

公开(公告)日：1991-10-08

申请号：US393085

申请日：1989-08-09

申请人： Thomas P. Duffy

发明人： Thomas P. Duffy

IPC分类号： B29C41/28 ,  B29C41/32 ,  B29C43/00 ,  E01C5/20 ,  E02D17/20

CPC分类号： E02D17/202 ,  B29C41/28 ,  B29C41/32 ,  B29C43/006 ,  E01C5/20

摘要： A porous, filamentary mat has a plurality of layers that are in intimate face-to-face relation and that have portions of the confronting faces thereof bonded together to enable those layers to constitute a unitary, porous, filamentary mat. Each of the layers has a plurality of elongated filaments of thermoplastic material; and each of those filaments is arranged in an essentially horizontal attitude and is longer than the mat. Each of those filaments has a number of bends therein which cause portions of each filament to cross and to engage other portions of that filament; and those bends also cause portions of each filament to cross and to engage portions of one or more adjacent filaments. The crossing portions of each filament, and the crossing portions of adjacent filaments, are bonded together by initial thermal bonds that are subsequently enhanced; as by pressing together the adjacent crossing portions of the various filaments of the mat while they are in a tacky state, by applying additional heat to the initially-thermally-bonded filaments of the mat to cause the initial thermal bonds to form longer and deeper bond, or by applying both heat and pressure to those initial thermal bonds.

摘要翻译： 多孔的丝状垫具有多个彼此紧密的面对面关系的层，并且其相对面的部分结合在一起以使得这些层能够构成一体的，多孔的丝状垫。 每个层都具有多根细长的热塑性材料长丝; 并且这些细丝中的每一根被布置成基本水平的姿态并且比垫长。 这些细丝中的每一根都具有多个弯曲部，其中每个细丝的一部分交叉并接合该长丝的其它部分; 并且这些弯曲也使得每个细丝的部分交叉并接合一个或多个相邻细丝的部分。 每个细丝的交叉部分和相邻长丝的交叉部分通过随后增强的初始热粘结而结合在一起; 通过将毡的各种长丝的相邻交叉部分压在一起，同时将它们处于粘性状态时，通过向垫的初始热粘合长丝施加额外的热量，以使初始热粘合形成更长更深的粘结 ，或通过对这些初始热粘合施加热和压力。

公开(公告)号：US20120101342A1

公开(公告)日：2012-04-26

申请号：US13276321

申请日：2011-10-19

申请人： Thomas P. Duffy ,  Gerald T. Harder ,  Kevin Mori

发明人： Thomas P. Duffy ,  Gerald T. Harder ,  Kevin Mori

IPC分类号： A61B1/06

CPC分类号： A61B5/489

摘要： A pediatric tissue illuminator includes a semi-rigid lighting head removably connected to a powered base unit for illuminating an infant's tissues while stabilizing a limb for venipuncture. The lighting head includes a series of LEDs and is placed behind an infant's arm, thereby directing light therethrough for enhanced viewing. A printed circuit board in the lighting head routes electrical conductors to the LEDs. A translucent soft covering is disposed between the printed circuit board and the infant's body. The base unit includes a control circuit for varying the application of electrical power to the lighting head via an electrical cable. The arm board/light head is inexpensive enough to be disposable. Alternatively, a re-useable light head may be used with disposable semi-rigid housings.

摘要翻译： 儿科组织照明器包括可移除地连接到动力基座单元上的半刚性照明头，用于照亮婴儿组织，同时稳定肢体以进行静脉穿刺。 照明头包括一系列LED并且被放置在婴儿的手臂后面，从而引导光通过以增强观看。 照明头中的印刷电路板将电导体引导到LED。 在印刷电路板和婴儿身体之间设置半透明的软覆盖物。 基座单元包括用于通过电缆改变对照明头的电功率的控制电路。 手臂板/灯头的价格足够便宜，可以一次性使用。 或者，可重复使用的光头可以与一次性半刚性外壳一起使用。

公开(公告)号：US5620782A

公开(公告)日：1997-04-15

申请号：US459929

申请日：1995-06-02

申请人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

发明人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

IPC分类号： H01R4/26 ,  H01R4/58 ,  H01R12/61 ,  H01R13/66 ,  H05K1/00 ,  H05K1/03 ,  H05K1/14 ,  H05K3/00 ,  H05K3/32 ,  H05K3/46 ,  B32B9/00

CPC分类号： H05K3/4635 ,  H01R12/613 ,  H01R13/665 ,  H05K3/462 ,  H01R4/26 ,  H01R4/58 ,  H05K1/0373 ,  H05K1/0393 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10159 ,  H05K3/328 ,  H05K3/4623 ,  H05K3/4641 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49179 ,  Y10T428/24917

摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the per fluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the per fluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.

摘要翻译： 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。 各个子组件的层压是通过低熔点粘合剂来实现的，该低熔点粘合剂与要层压的区域中的子组件之间的每个碳氟化合物聚合物化学相容（可粘合），以及任选的与化学不相容的高熔点掩模 不能粘合）在不想层压的区域中的子组件之间的每个碳氟聚合物。 加热组件叠层以选择性地在要层压的区域中进行粘合和层压，同时避免在不想层压的区域中层压。

公开(公告)号：US5566448A

公开(公告)日：1996-10-22

申请号：US470389

申请日：1995-06-06

申请人： Ashwinkumar C. Bhatt ,  Thomas P. Duffy ,  Jeffrey A. Knight ,  James P. Walsh

发明人： Ashwinkumar C. Bhatt ,  Thomas P. Duffy ,  Jeffrey A. Knight ,  James P. Walsh

IPC分类号： H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H05K3/34

CPC分类号： H01L23/5385 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49833 ,  H01L2224/48091 ,  H01L2224/48227 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method of forming an I/C chip mounting module, and for mounting an I/C chip thereon, is disclosed. A rigid cap and substrate are provided. A bottomed cavity is routed in the cap, and the substrate has circuitry formed thereon. The cap and substrate are laminated together with bond pads, which connect to the circuitry being disposed in the cavity. After circuitization of the exposed surface of the cap and drilling and plating of vias, the material of the cap overlying the cavity is removed to expose the bond pads. Thereafter, an I/C chip is connect to the pads.

摘要翻译： 公开了一种形成I / C芯片安装模块和用于在其上安装I / C芯片的方法。 提供了刚性帽和衬底。 有底的空腔在盖中布线，并且基板具有形成在其上的电路。 帽和衬底与连接到设置在空腔中的电路连接的接合焊盘层压在一起。 在盖的暴露表面电路化和通孔的钻孔和电镀之后，去除覆盖空腔的盖的材料以露出接合焊盘。 此后，I / C芯片连接到焊盘。

公开(公告)号：US5509196A

公开(公告)日：1996-04-23

申请号：US310190

申请日：1994-09-21

申请人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

发明人： Charles R. Davis ,  Thomas P. Duffy ,  Steven L. Hanakovic ,  Howard L. Heck ,  John T. Kolias ,  John S. Kresge ,  David N. Light ,  Ajit K. Trivedi

IPC分类号： H01R4/26 ,  H01R4/58 ,  H01R12/61 ,  H01R13/66 ,  H05K1/00 ,  H05K1/03 ,  H05K1/14 ,  H05K3/00 ,  H05K3/32 ,  H05K3/46 ,  H05K3/36 ,  H05K3/20

CPC分类号： H05K3/4635 ,  H01R12/613 ,  H01R13/665 ,  H05K3/462 ,  H01R4/26 ,  H01R4/58 ,  H05K1/0373 ,  H05K1/0393 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10159 ,  H05K3/328 ,  H05K3/4623 ,  H05K3/4641 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49179 ,  Y10T428/24917

摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.

摘要翻译： 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 各个子组件的层压是通过与要层压的区域中的子组件之间的全氟化碳聚合物化学相容（可粘合）化学相容的低熔点粘合剂，以及任选的与化学不相容的高熔点掩模 可粘合到）在不想层压的区域中的子组件之间的全氟化碳聚合物。 加热组件叠层以选择性地在要层压的区域中进行粘合和层压，同时避免在不想层压的区域中层压。

公开(公告)号：US5460921A

公开(公告)日：1995-10-24

申请号：US118010

申请日：1993-09-08

申请人： Douglas A. Cywar ,  Charles R. Davis ,  Thomas P. Duffy ,  Frank D. Egitto ,  Paul J. Hart ,  Gerald W. Jones ,  Edward McLeskey

发明人： Douglas A. Cywar ,  Charles R. Davis ,  Thomas P. Duffy ,  Frank D. Egitto ,  Paul J. Hart ,  Gerald W. Jones ,  Edward McLeskey

IPC分类号： G03F7/00 ,  H05K1/09 ,  H05K3/00 ,  H05K3/10 ,  H05K3/12 ,  H05K3/40 ,  H05K3/46 ,  G03C5/00

CPC分类号： G03F7/00 ,  H05K3/0032 ,  H05K3/1258 ,  H05K3/4069 ,  H05K1/095 ,  H05K2201/015 ,  H05K2201/0209 ,  H05K2203/0191 ,  H05K2203/0568 ,  H05K2203/0769 ,  H05K2203/0783 ,  H05K2203/1383 ,  H05K3/0035 ,  H05K3/107 ,  H05K3/4664 ,  Y10S428/901 ,  Y10S430/146 ,  Y10T428/24917

摘要： The present invention provides a method of ablative photodecomposition and forming metal pattern which attains high resolution, is convenient, and employs non-halogenated solvents. The present invention is directed to a process for forming a metal pattern, preferably circuitization on an organic substrate, preferably on a circuit board or component thereof, which comprises coating the substrate with an ablatively-removable coating comprising a polymer resin preferably an acrylate polymer resin and preferably an ultraviolet absorber. A pattern is formed in the polymer coating corresponding to the desired metal pattern by irradiating at least a portion of the polymer coating with a sufficient amount of ultraviolet radiation to thereby ablatively remove the irradiated portion of the polymer coating. Next the patterned substrate is coated with a conductive metal paste to define the metal pattern, and the conductive metal paste is cured. The remaining polymer coating is removed by solvent stripping with non-halogenated solvents. The present invention further includes patterning electronic structures comprising multilayer circuitry using the above method. An excimer laser is used to form vias or through holes in the electronic structure while simultaneously patterning the polymer coating. This results in perfect alignment between the pattern formed in the polymer coating and the vias or through holes. High resolution circuitry is thus attainable when the electronic structure is subsequently metallized with a conductive metal paste.

摘要翻译： 本发明提供了一种烧蚀光分解和形成金属图案的方法，其获得高分辨率，方便并采用非卤化溶剂。 本发明涉及一种用于形成金属图案的方法，优选在有机基板上，优选在电路板或其组件上进行电路化，该方法包括用可剥离涂层涂覆基材，该涂层包含聚合物树脂，优选丙烯酸酯聚合物树脂 优选紫外线吸收剂。 通过用足够量的紫外线照射至少一部分聚合物涂层，形成对应于所需金属图案的聚合物涂层中的图案，从而消除聚合物涂层的照射部分。 接下来，用导电金属膏涂覆图案化衬底以限定金属图案，并且导电金属膏被固化。 通过用非卤化溶剂的溶剂汽提除去剩余的聚合物涂层。 本发明还包括使用上述方法图案化包括多层电路的电子结构。 准分子激光器用于在电子结构中形成通孔或通孔，同时构图聚合物涂层。 这导致在聚合物涂层中形成的图案与通孔或通孔之间完美对准。 因此，当电子结构随后用导电金属膏进行金属化时，可实现高分辨率电路。

公开(公告)号：US07002249B2

公开(公告)日：2006-02-21

申请号：US10294423

申请日：2002-11-12

申请人： Thomas P. Duffy ,  John Ryan Goodfellow ,  Robert T. Carroll ,  Kevin J. Cote ,  Sampath K. V. Karikalan ,  Suresh Golwalkar

发明人： Thomas P. Duffy ,  John Ryan Goodfellow ,  Robert T. Carroll ,  Kevin J. Cote ,  Sampath K. V. Karikalan ,  Suresh Golwalkar

IPC分类号： H01L23/495 ,  H01L27/02 ,  H01L23/48

CPC分类号： H01L24/85 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49052 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  Y10S257/916 ,  H01L2924/01004 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45147 ,  H01L2924/0132 ,  H01L2924/2075 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00011

摘要： A semiconductor device package is disclosed which includes inter-digitated input and output bond wires configured to increase the negative mutual inductive coupling between the wires, thus reducing the overall parasitic inductance of the device. In one embodiment, the microelectronic component includes a semiconductor device coupled to a substrate, such as a lead frame, a first set of bond wires connected to the semiconductor device for providing current flow into the semiconductor device, and a second set of bond wires that are in a current loop with the first set of bond wires and are connected to the semiconductor device for providing current flow out of the semiconductor device, wherein the first and second set of bond wires are configured in an inter-digitated pattern to increase the magnitude of mutual inductive coupling between the first and second set of bond wires. In one embodiment, the semiconductor device comprises a single semiconductor chip and the lead frame comprises a Quad Flat No-Lead (QFN) lead frame. Other embodiments include multiple chips and/or multiple lead frames.

摘要翻译： 公开了一种半导体器件封装，其包括配置为增加导线之间的负互感耦合的数字化输入和输出接合线，从而减小器件的总体寄生电感。 在一个实施例中，微电子部件包括耦合到诸如引线框架的基板的半导体器件，连接到半导体器件的用于提供电流流入半导体器件的第一组接合线，以及第二组接合线， 与第一组接合线处于电流回路中并且连接到半导体器件，用于提供从半导体器件流出的电流，其中第一组和第二组接合线被配置为数字化的图案以增加幅度 的第一组和第二组接合线之间的互感耦合。 在一个实施例中，半导体器件包括单个半导体芯片，并且引线框架包括四边形扁平无引线（QFN）引线框架。 其他实施例包括多个芯片和/或多个引线框架。

公开(公告)号：US06674320B2

公开(公告)日：2004-01-06

申请号：US09978613

申请日：2001-10-16

申请人： Thomas P. Duffy ,  Yi Zhang ,  Malay Trivedi

发明人： Thomas P. Duffy ,  Yi Zhang ,  Malay Trivedi

IPC分类号： H03B100

CPC分类号： H01F29/14

摘要： A control system, method and apparatus is provided for an orthogonally variable inductor. A method and apparatus is also provided for voltage regulation. Regulation is provided without the use of Silicon devices, such as FET's, in the output current path. Efficient voltage regulation is provided via varying the inductance of a device in the output current path, and alternatively via varying the inductance and duty cycle. An orthogonal inductive device is provided to vary the inductance in the output current path. The orthogonal inductive device is an external H field device, a series method orthogonal flux device, or a combined core device. Furthermore, a variable inductor is also provided in filters, amplifiers, and oscillators.

摘要翻译： 提供了一种用于正交可变电感器的控制系统，方法和装置。 还提供了用于电压调节的方法和装置。 在输出电流路径中不使用诸如FET的硅器件提供调节。 通过改变输出电流路径中的器件的电感，或者通过改变电感和占空比来提供有效的电压调节。 提供正交感应装置以改变输出电流路径中的电感。 正交电感器件是外部H场器件，串联方法正交通量器件或组合核心器件。 此外，滤波器，放大器和振荡器中还提供可变电感器。