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    DRIVE UNIT FOR ELECTRIC BICYCLE
    1.
    发明申请
    DRIVE UNIT FOR ELECTRIC BICYCLE 审中-公开
    电动自行车驱动装置

    公开(公告)号：US20150148173A1

    公开(公告)日：2015-05-28

    申请号：US14109891

    申请日：2013-12-17

    申请人： Il Ryong Kim ,  Seong Jong Cho

    发明人： Il Ryong Kim ,  Seong Jong Cho

    IPC分类号： H02K7/116 ,  B62K11/00

    CPC分类号： H02K7/116 ,  B62K15/006 ,  B62M6/65 ,  B62M11/18

    摘要： A drive unit for an electric bicycle, the drive unit including a motor configured to generate a rotary force to drive a wheel of the electric bicycle, and a reduction gear unit provided with a plurality of gears to decelerate a rotary force generated from the motor, wherein the motor is provided with a rotor which has an accommodation space formed at a center thereof and a stator installed to surround the rotor while being spaced apart from the rotor by a predetermined interval, and the reduction gear unit includes a first planet gear assembly disposed on an accommodation space inside the motor and connected to the rotor, and a second planet gear assembly disposed outside the motor and connected to the first planet gear assembly.

    摘要翻译： 一种用于电动自行车的驱动单元，所述驱动单元包括：电动机，其构造成产生用于驱动所述电动自行车的车轮的旋转力;以及减速齿轮单元，其具有多个齿轮以减速从所述电动机产生的旋转力， 其特征在于，所述电动机具有转子，所述转子具有形成在其中心的容置空间，以及定子，所述转子围绕所述转子安装以与所述转子隔开预定间隔，所述减速齿轮单元包括：第一行星齿轮组件， 在电动机内部并且连接到转子上的容纳空间以及设置在电动机外部并连接到第一行星齿轮组件的第二行星齿轮组件。

    Metal-insulator-metal (MIM) capacitor and method of fabricating the same
    3.
    发明授权
    Metal-insulator-metal (MIM) capacitor and method of fabricating the same 有权
    金属绝缘体金属（MIM）电容器及其制造方法

    公开(公告)号：US07332764B2

    公开(公告)日：2008-02-19

    申请号：US11080567

    申请日：2005-03-16

    申请人： Seung-Man Choi ,  Ki-Chul Park ,  Bong-Seok Suh ,  Il-Ryong Kim

    发明人： Seung-Man Choi ,  Ki-Chul Park ,  Bong-Seok Suh ,  Il-Ryong Kim

    IPC分类号： H01L29/76

    CPC分类号： H01L21/76841 ,  H01L21/76846 ,  H01L21/7685 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric layer covering the lower metal interconnection, the lower metal electrode, and the interlayer insulating layer, a via hole exposing the lower metal interconnection, an upper metal interconnection groove crossing over the via hole, at least one capacitor trench region exposing the lower metal electrode, an upper metal interconnection filling the upper metal interconnection groove, the upper metal interconnection being electrically connected to the lower metal interconnection through the via hole, a dielectric layer covering inner surfaces of the at least one capacitor trench region, and an upper metal electrode surrounded by the dielectric layer to fill the at least one capacitor trench region.

    摘要翻译： 在MIM电容器及其制造方法中，MIM电容器包括在半导体衬底上的层间绝缘层，层间绝缘层中的下部金属互连和下部金属电极，覆盖下部金属互连的金属间介电层， 下金属电极和层间绝缘层，暴露下金属互连的通孔，与通孔相交的上金属互连槽，暴露下金属电极的至少一个电容器沟槽区，填充上金属互连的上金属互连 金属互连槽，所述上金属互连通过所述通孔电连接到所述下金属互连，覆盖所述至少一个电容器沟槽区的内表面的电介质层和被所述电介质层包围的上金属电极以填充 至少一个电容器沟槽区域。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20100224939A1

    公开(公告)日：2010-09-09

    申请号：US12716914

    申请日：2010-03-03

    申请人： Ju-youn Kim ,  Bong-seok Kim ,  Il-ryong Kim ,  Cheong-sik Yu ,  Ki-young Kim ,  Yu-jin Jeon

    发明人： Ju-youn Kim ,  Bong-seok Kim ,  Il-ryong Kim ,  Cheong-sik Yu ,  Ki-young Kim ,  Yu-jin Jeon

    IPC分类号： H01L27/092 ,  H01L29/78

    CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/51 ,  H01L29/78

    摘要： Provided is a metal-oxide semiconductor (MOS) transistor containing a metal gate pattern. The semiconductor device includes a p-channel metal-oxide semiconductor (PMOS) transistor including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first metal gate conductive film formed on the first insulating film, and a nitrogen diffusion blocking film formed between the first insulating film and the first metal gate conductive film, and an n-channel metal-oxide semiconductor (NMOS) transistor including the semiconductor substrate, a second insulating film formed on the semiconductor substrate, a second metal gate conductive film formed on the second insulating film, and a reaction blocking film formed of metal nitride and formed between the second insulating film and the second metal gate conductive film. According to the inventive concept, a reaction between a metal gate film and an insulating film may be minimized so as to result in a highly reliable MOS transistor.

    摘要翻译： 提供了含有金属栅极图案的金属氧化物半导体（MOS）晶体管。 半导体器件包括：包括半导体衬底的p沟道金属氧化物半导体（PMOS）晶体管，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的第一金属栅极导电膜，以及氮扩散阻挡膜 形成在第一绝缘膜和第一金属栅极导电膜之间，以及包括半导体衬底的n沟道金属氧化物半导体（NMOS）晶体管，形成在半导体衬底上的第二绝缘膜，形成在第一绝缘膜上的第二金属栅极导电膜 第二绝缘膜和由金属氮化物形成并形成在第二绝缘膜和第二金属栅极导电膜之间的反应阻挡膜。 根据本发明构思，可以使金属栅极膜和绝缘膜之间的反应最小化，从而导致高度可靠的MOS晶体管。

    Metal-insulator-metal (MIM) capacitor and method of fabricating the same
    6.
    发明申请
    Metal-insulator-metal (MIM) capacitor and method of fabricating the same 有权
    金属绝缘体金属（MIM）电容器及其制造方法

    公开(公告)号：US20050275005A1

    公开(公告)日：2005-12-15

    申请号：US11080567

    申请日：2005-03-16

    申请人： Seung-Man Choi ,  Ki-Chul Park ,  Bong-Seok Suh ,  Il-Ryong Kim

    发明人： Seung-Man Choi ,  Ki-Chul Park ,  Bong-Seok Suh ,  Il-Ryong Kim

    IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/52 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108 ,  H01L29/76

    CPC分类号： H01L21/76841 ,  H01L21/76846 ,  H01L21/7685 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric layer covering the lower metal interconnection, the lower metal electrode, and the interlayer insulating layer, a via hole exposing the lower metal interconnection, an upper metal interconnection groove crossing over the via hole, at least one capacitor trench region exposing the lower metal electrode, an upper metal interconnection filling the upper metal interconnection groove, the upper metal interconnection being electrically connected to the lower metal interconnection through the via hole, a dielectric layer covering inner surfaces of the at least one capacitor trench region, and an upper metal electrode surrounded by the dielectric layer to fill the at least one capacitor trench region.

    摘要翻译： 在MIM电容器及其制造方法中，MIM电容器包括在半导体衬底上的层间绝缘层，层间绝缘层中的下部金属互连和下部金属电极，覆盖下部金属互连的金属间介电层， 下金属电极和层间绝缘层，暴露下金属互连的通孔，与通孔相交的上金属互连槽，暴露下金属电极的至少一个电容器沟槽区，填充上金属互连的上金属互连 金属互连槽，所述上金属互连通过所述通孔电连接到所述下金属互连，覆盖所述至少一个电容器沟槽区的内表面的电介质层和被所述电介质层包围的上金属电极以填充 至少一个电容器沟槽区域。

    Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby
    7.
    发明申请
    Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby 有权
    通过选择性地形成扩散阻挡层制造半导体器件的方法和由此制造半导体器件

    公开(公告)号：US20050153544A1

    公开(公告)日：2005-07-14

    申请号：US11033189

    申请日：2005-01-11

    申请人： Bong-Seok Suh ,  Ki-Chul Park ,  Seung-Man Choi ,  Il-Ryong Kim

    发明人： Bong-Seok Suh ,  Ki-Chul Park ,  Seung-Man Choi ,  Il-Ryong Kim

    IPC分类号： H01L21/3205 ,  H01L21/285 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52

    CPC分类号： H01L21/76844 ,  H01L21/2855

    摘要： In a method of fabricating a semiconductor device by selectively forming a diffusion barrier layer, and a semiconductor device fabricated thereby, a conductive pattern and an insulating layer, which covers the conductive pattern, are formed on a semiconductor substrate. The insulating layer is patterned, thereby forming an opening for exposing at least a portion of the conductive pattern. Then, a diffusion barrier layer is formed on the semiconductor substrate having the opening, using a selective deposition technique. The diffusion barrier layer is formed to a thickness that is less on the exposed conductive pattern than the thickness of the diffusion barrier layer on the insulating layer exposed inside the opening. Then, the diffusion barrier layer is etched, thereby forming a recessed diffusion barrier layer. In this manner, metal atoms are prevented from being diffused from a metal plug filling the opening or a metal interconnect to the insulating layer.

    摘要翻译： 在通过选择性地形成扩散阻挡层制造半导体器件的方法及其制造的半导体器件中，在半导体衬底上形成覆盖导电图案的导电图案和绝缘层。 对绝缘层进行图案化，从而形成用于暴露导电图案的至少一部分的开口。 然后，使用选择性沉积技术在具有开口的半导体衬底上形成扩散阻挡层。 扩散阻挡层形成为暴露在导体图案上的厚度小于暴露在开口内部的绝缘层上的扩散阻挡层的厚度。 然后，对扩散阻挡层进行蚀刻，从而形成凹陷扩散阻挡层。 以这种方式，防止金属原子从填充开口的金属插塞或与绝缘层的金属互连扩散。

    Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby
    8.
    发明授权
    Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby 有权
    通过选择性地形成扩散阻挡层制造半导体器件的方法和由此制造半导体器件

    公开(公告)号：US07335590B2

    公开(公告)日：2008-02-26

    申请号：US11033189

    申请日：2005-01-11

    申请人： Bong-Seok Suh ,  Ki-Chul Park ,  Seung-Man Choi ,  Il-Ryong Kim

    发明人： Bong-Seok Suh ,  Ki-Chul Park ,  Seung-Man Choi ,  Il-Ryong Kim

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76844 ,  H01L21/2855

    摘要： In a method of fabricating a semiconductor device by selectively forming a diffusion barrier layer, and a semiconductor device fabricated thereby, a conductive pattern and an insulating layer, which covers the conductive pattern, are formed on a semiconductor substrate. The insulating layer is patterned, thereby forming an opening for exposing at least a portion of the conductive pattern. Then, a diffusion barrier layer is formed on the semiconductor substrate having the opening, using a selective deposition technique. The diffusion barrier layer is formed to a thickness that is less on the exposed conductive pattern than the thickness of the diffusion barrier layer on the insulating layer exposed inside the opening. Then, the diffusion barrier layer is etched, thereby forming a recessed diffusion barrier layer. In this manner, metal atoms are prevented from being diffused from a metal plug filling the opening or a metal interconnect to the insulating layer.

    摘要翻译： 在通过选择性地形成扩散阻挡层制造半导体器件的方法及其制造的半导体器件中，在半导体衬底上形成覆盖导电图案的导电图案和绝缘层。 对绝缘层进行图案化，从而形成用于暴露导电图案的至少一部分的开口。 然后，使用选择性沉积技术在具有开口的半导体衬底上形成扩散阻挡层。 扩散阻挡层形成为暴露在导电图案上的厚度小于暴露在开口内部的绝缘层上的扩散阻挡层的厚度。 然后，对扩散阻挡层进行蚀刻，从而形成凹陷扩散阻挡层。 以这种方式，防止金属原子从填充开口的金属插塞或与绝缘层的金属互连扩散。