公开(公告)号：US08710657B2

公开(公告)日：2014-04-29

申请号：US13242864

申请日：2011-09-23

Applicant: Jeong-woo Park ,  Moon-gi Cho ,  Ui-hyoung Lee ,  Sun-hee Park

Inventor： Jeong-woo Park ,  Moon-gi Cho ,  Ui-hyoung Lee ,  Sun-hee Park

IPC: H01L21/44

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/13193 ,  H01L2224/14051 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01052 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Abstract translation: 提供了通过凸块将半导体芯片连接到外部设备的半导体封装。 半导体封装可以包括半导体芯片上的连接焊盘，连接焊盘，并且构造成电连接到连接焊盘，并且在半导体芯片上具有支撑突起，并且被配置为与连接焊盘电隔离。 连接凸起可以包括第一柱和第一焊球，并且支撑凸起可以包括第二柱和第二焊球。 半导体封装还可以包括在第二柱中的焊料通道，其被配置为允许第二焊球的一部分沿着预定方向延伸到焊料通道中。

公开(公告)号：US20120292195A1

公开(公告)日：2012-11-22

申请号：US13438020

申请日：2012-04-03

Applicant: Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

Inventor： Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

IPC: C25B15/00 ,  C25B9/00

CPC classification number: C25D17/001 ,  C25D5/02 ,  C25D5/08 ,  C25D7/123 ,  C25D17/008 ,  H01L21/2885

Abstract: An apparatus for electroplating a semiconductor device includes a plating bath accommodating a plating solution, and a paddle in the plating bath, the paddle including a plurality of holes configured to pass the plating solution through the paddle toward a substrate, and a plating solution flow reinforcement portion configured to selectively reinforce a flow of the plating solution to a predetermined area of the substrate, the predetermined area of the substrate being an area requiring a relatively increased supply of metal ions of the plating solution.

Abstract translation: 一种用于电镀半导体器件的设备包括一个容纳电镀溶液的电镀液和一个在电镀槽中的一个电极板，该电极板包括多个孔，该多个孔被配置成将电镀液通过桨向衬底通过，电镀液流动加强 所述部分被配置为选择性地将所述电镀溶液的流动加强到所述基板的预定区域，所述基板的所述预定区域是需要相对增加所述电镀液的金属离子供应的区域。

公开(公告)号：US20120086123A1

公开(公告)日：2012-04-12

申请号：US13242864

申请日：2011-09-23

Applicant: JEONG-WOO PARK ,  MOON-GI CHO ,  UI-HYOUNG LEE ,  SUN-HEE PARK

Inventor： JEONG-WOO PARK ,  MOON-GI CHO ,  UI-HYOUNG LEE ,  SUN-HEE PARK

IPC: H01L23/498

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/13193 ,  H01L2224/14051 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01052 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Abstract translation: 提供了通过凸块将半导体芯片连接到外部设备的半导体封装。 半导体封装可以包括半导体芯片上的连接焊盘，连接焊盘，并且构造成电连接到连接焊盘，并且在半导体芯片上具有支撑突起，并且被配置为与连接焊盘电隔离。 连接凸起可以包括第一柱和第一焊球，并且支撑凸起可以包括第二柱和第二焊球。 半导体封装还可以包括在第二柱中的焊料通道，其被配置为允许第二焊球的一部分沿着预定方向延伸到焊料通道中。

公开(公告)号：US07807337B2

公开(公告)日：2010-10-05

申请号：US11968787

申请日：2008-01-03

Applicant: Hyo-Jong Lee ,  Hong-Seong Son ,  Ui-Hyoung Lee ,  Sang-Rok Hah ,  In-Ryong Kim ,  Yi-Gwon Kim

Inventor： Hyo-Jong Lee ,  Hong-Seong Son ,  Ui-Hyoung Lee ,  Sang-Rok Hah ,  In-Ryong Kim ,  Yi-Gwon Kim

IPC: G03F7/26

CPC classification number: H01L28/10 ,  H01F41/041 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.

Abstract translation: 公开了一种用于片上系统的电感器和用于制造电感器的方法。 电感器包括通过连接从形成在下布线上的晶种层生长的多个导电图案而形成的导电线。 该方法包括使用电解电镀工艺或无电镀处理，以从种子层生长多个相邻的导电图案直到它们连接。 该方法还能够将导线的高度和宽度调整到所希望的水平。

公开(公告)号：US20070059923A1

公开(公告)日：2007-03-15

申请号：US11445458

申请日：2006-06-02

Applicant: Hyo-jong Lee ,  Ui-hyoung Lee ,  Hong-jae Shin ,  Nae-in Lee ,  Soo-geun Lee

Inventor： Hyo-jong Lee ,  Ui-hyoung Lee ,  Hong-jae Shin ,  Nae-in Lee ,  Soo-geun Lee

IPC: H01L21/4763

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843

Abstract: Methods of fabricating an interconnection line in a semiconductor device and a semiconductor device including such an interconnection line. The method involves forming a lower interconnection line on a semiconductor substrate, forming a mold pattern that defines an opening through which the lower interconnection line is exposed, filling the opening with a conductive material to form a via, removing the mold pattern to make the via remain on the lower interconnection line, forming an interlevel dielectric (ILD) layer that covers the lower interconnection line and the via, patterning the ILD layer, exposing the via, forming a trench that defines a region in which an interconnection line is to be formed, and filling the trench to fabricate a damascene interconnection line connected to the via.

Abstract translation: 在半导体器件中制造互连线的方法和包括这种互连线的半导体器件。 该方法包括在半导体衬底上形成下部互连线，形成限定下部互连线暴露的开口的模具图案，用导电材料填充开口以形成通孔，去除模具图案以形成通孔 保持在下互连线上，形成覆盖下互连线和通孔的层间电介质（ILD）层，图案化ILD层，暴露通孔，形成限定要形成互连线的区域的沟槽 ，并填充沟槽以制造连接到通孔的镶嵌互连线。

公开(公告)号：US20050116317A1

公开(公告)日：2005-06-02

申请号：US10982782

申请日：2004-11-08

Applicant: Hyo-Jong Lee ,  Hong-Seong Son ,  Ui-Hyoung Lee ,  Sang-Rok Hah ,  Il-Ryong Kim ,  Yi-Gwon Kim

Inventor： Hyo-Jong Lee ,  Hong-Seong Son ,  Ui-Hyoung Lee ,  Sang-Rok Hah ,  Il-Ryong Kim ,  Yi-Gwon Kim

IPC: H01L27/04 ,  H01F17/00 ,  H01F41/04 ,  H01L21/02 ,  H01L23/522 ,  H01L27/08 ,  H01L21/00 ,  H01L21/4763 ,  H01L21/8238 ,  H01L29/00

CPC classification number: H01L28/10 ,  H01F41/041 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.

Abstract translation: 公开了一种用于片上系统的电感器和用于制造电感器的方法。 电感器包括通过连接从形成在下布线上的晶种层生长的多个导电图案而形成的导电线。 该方法包括使用电解电镀工艺或无电镀处理，以从种子层生长多个相邻的导电图案直到它们连接。 该方法还能够将导线的高度和宽度调整到所希望的水平。

公开(公告)号：US20120129333A1

公开(公告)日：2012-05-24

申请号：US13241824

申请日：2011-09-23

Applicant: Ha-Young YIM ,  Eun-Chul AHN ,  Ui-Hyoung LEE ,  Moon-Gi CHO ,  Hwan-Sik LIM

Inventor： Ha-Young YIM ,  Eun-Chul AHN ,  Ui-Hyoung LEE ,  Moon-Gi CHO ,  Hwan-Sik LIM

IPC: H01L21/60 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/76804 ,  H01L21/76885 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11912 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014

Abstract: Provided are a method for manufacturing a semiconductor package and a semiconductor package manufactured using the method. The method includes providing a substrate having a first region and a second region having a higher step difference than the first region, i.e., having a difference in height, forming a mask pattern having a first opening exposing a portion of the first region and a second opening exposing a portion of the second region on the substrate, forming first and second bump material films filling the first and second openings, respectively, and forming the first and second bumps by performing a reflow process on the first and second bump material films, wherein the first opening has a lower portion having the same width with the second opening and a top portion having a width greater than the second opening.

Abstract translation: 提供一种使用该方法制造的半导体封装和半导体封装的制造方法。 该方法包括提供具有第一区域和第二区域的衬底，该第一区域和第二区域具有比第一区域更高的台阶差，即，具有高度差，形成具有暴露第一区域的一部分的第一开口的掩模图案， 打开所述基板上的所述第二区域的一部分，分别形成填充所述第一和第二开口的第一和第二凸块材料膜，并且通过对所述第一和第二凸块材料膜执行回流处理来形成所述第一和第二凸块，其中 第一开口具有与第二开口具有相同宽度的下部，并且具有大于第二开口的宽度的顶部。

公开(公告)号：US09082680B2

公开(公告)日：2015-07-14

申请号：US13535766

申请日：2012-06-28

Applicant: Ju-Il Choi ,  Jeong-Gi Jin ,  Ui-Hyoung Lee ,  Hyung-Seok Kim ,  Jeong-Woo Park

Inventor： Ju-Il Choi ,  Jeong-Gi Jin ,  Ui-Hyoung Lee ,  Hyung-Seok Kim ,  Jeong-Woo Park

IPC: H05K1/16 ,  H05K1/18 ,  H01L23/00 ,  H05K3/34 ,  B23K1/00 ,  H01L25/065 ,  H01L25/10 ,  H05K3/40 ,  H01L23/31

CPC classification number: H01L24/16 ,  B23K1/0016 ,  B23K2101/42 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/13 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2224/13686 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/181 ,  H05K3/3442 ,  H05K3/3489 ,  H05K3/4007 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/053 ,  H01L2924/00012

Abstract: The inventive concept provides methods for inhibiting the formation of one or more oxides on metal bumps during the formation of solder joint structures and solder joint structures including one or more preservative films. In some embodiments, the solder joint structure includes a metal bump having a preservative film disposed on the surface thereof.

Abstract translation: 本发明构思提供了在形成包括一个或多个防腐膜的焊接结构和焊点结构期间，抑制在金属凸块上形成一种或多种氧化物的方法。 在一些实施例中，焊点结构包括具有设置在其表面上的防腐膜的金属凸块。

公开(公告)号：US20130000978A1

公开(公告)日：2013-01-03

申请号：US13535766

申请日：2012-06-28

Applicant: Ju-Il Choi ,  Jeong-Gi Jin ,  Ui-Hyoung Lee ,  Hyung-Seok Kim ,  Jeong-Woo Park

Inventor： Ju-Il Choi ,  Jeong-Gi Jin ,  Ui-Hyoung Lee ,  Hyung-Seok Kim ,  Jeong-Woo Park

IPC: H01R4/02

CPC classification number: H01L24/16 ,  B23K1/0016 ,  B23K2101/42 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/13 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2224/13686 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/181 ,  H05K3/3442 ,  H05K3/3489 ,  H05K3/4007 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/053 ,  H01L2924/00012

Abstract: The inventive concept provides methods for inhibiting the formation of one or more oxides on metal bumps during the formation of solder joint structures and solder joint structures including one or more preservative films. In some embodiments, the solder joint structure includes a metal bump having a preservative film disposed on the surface thereof.

Abstract translation: 本发明构思提供了在形成包括一个或多个防腐膜的焊接结构和焊点结构期间，抑制在金属凸块上形成一种或多种氧化物的方法。 在一些实施例中，焊点结构包括具有设置在其表面上的防腐膜的金属凸块。

公开(公告)号：US08183673B2

公开(公告)日：2012-05-22

申请号：US12565969

申请日：2009-09-24

Applicant: Son-Kwan Hwang ,  Keum-Hee Ma ,  Seung-Woo Shin ,  Min-Seung Yoon ,  Jong-Ho Yun ,  Ui-Hyoung Lee

Inventor： Son-Kwan Hwang ,  Keum-Hee Ma ,  Seung-Woo Shin ,  Min-Seung Yoon ,  Jong-Ho Yun ,  Ui-Hyoung Lee

IPC: H01L23/495

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/30105 ,  H01L2224/05552

Abstract: A microelectronic device structure as provided herein includes a conductive via having a body portion extending into a substrate from an upper surface thereof and a connecting portion laterally extending along the upper surface of the substrate. The connecting portion includes a recess therein opposite the upper surface of the substrate. The recess is confined within the connecting portion of the conductive via and does not extend beneath the upper surface of the substrate. A microelectronic device structure is also provided that includes a conductive via having a body portion extending into a substrate from an upper surface thereof and an end portion below the upper surface of the substrate. The end portion has a greater width than that of the body portion. A solder wettable layer is provided on the end portion. The solder wettable layer is formed of a material having a greater wettability with a conductive metal than that of the end portion of conductive via. Related methods of fabrication are also discussed.

Abstract translation: 如本文提供的微电子器件结构包括导电通孔，其导体通孔具有从其上表面延伸到衬底中的主体部分和沿衬底的上表面横向延伸的连接部分。 连接部分包括与衬底的上表面相对的凹部。 凹槽被限制在导电通孔的连接部分内，并且不延伸到衬底的上表面之下。 还提供了一种微电子器件结构，其包括导电通孔，该导电通孔具有从其上表面延伸到衬底中的主体部分和位于衬底的上表面下方的端部。 端部具有比主体部分宽的宽度。 在端部设置焊料可湿性层。 焊料可湿性层由导电金属具有比导电通孔的端部润湿性更高的润湿性的材料形成。 还讨论了相关的制造方法。