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    Methods of fabricating a semiconductor device
    1.
    发明申请
    Methods of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20090155991A1

    公开(公告)日：2009-06-18

    申请号：US12292195

    申请日：2008-11-13

    申请人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/6653

    摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.

    摘要翻译： 提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如 层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

    Chemical mechanical polishing slurry and chemical mechanical polishing method using the same
    3.
    发明授权
    Chemical mechanical polishing slurry and chemical mechanical polishing method using the same 有权
    化学机械抛光浆料和化学机械抛光方法使用相同

    公开(公告)号：US06887137B2

    公开(公告)日：2005-05-03

    申请号：US10378102

    申请日：2003-02-28

    申请人： Jae-dong Lee ,  Bo-un Yoon ,  Yong-pil Han

    发明人： Jae-dong Lee ,  Bo-un Yoon ,  Yong-pil Han

    IPC分类号： B24B37/00 ,  C09G1/02 ,  C09K3/14 ,  C09K13/06 ,  H01L21/304 ,  H01L21/3105 ,  C09K13/00

    CPC分类号： H01L21/31053 ,  C09G1/02

    摘要： Slurries for chemical mechanical polishing (CMP) are provided including a high planarity slurry and high selectivity ratio slurry. A high planarity slurry includes at least one kind of metal oxide abrasive particle and an anionic polymer passivation agent having a first concentration. A high selectivity ratio slurry includes at least one kind of the metal oxide abrasive particle, the passivation agent in a second concentration that is less than the first concentration of the passivation agent for the high planarity slurry, one of a quaternary amine and the salt thereof, and a pH control agent. The high selectivity ratio slurry has a pH in a range of about over an isoelectric point of a polishing target layer and less than an isoelectric point of a polishing stopper. In addition, a CMP method using the CMP slurries having high planarity and high selectivity ratio is provided.

    摘要翻译： 提供用于化学机械抛光（CMP）的浆料，其包括高平坦度浆料和高选择比浆料。 高平坦度浆料包括至少一种金属氧化物磨料颗粒和具有第一浓度的阴离子聚合物钝化剂。 高选择比浆料包括至少一种金属氧化物磨料颗粒，第二浓度的钝化剂小于高平坦度浆料的钝化剂的第一浓度，季胺及其盐之一 ，和pH控制剂。 高选择比浆料的pH在大约等于抛光对象层的等电点的范围内且小于抛光终止体的等电点。 此外，提供了使用具有高平坦度和高选择比的CMP浆料的CMP方法。

    Test patterns and methods of controlling CMP process using the same
    5.
    发明授权
    Test patterns and methods of controlling CMP process using the same 失效
    使用该方法控制CMP工艺的测试模式和方法

    公开(公告)号：US06875997B2

    公开(公告)日：2005-04-05

    申请号：US10396595

    申请日：2003-03-25

    申请人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L21/66 ,  C03C25/68 ,  C23F1/00 ,  G01R31/26 ,  H01L21/4763 ,  H01L23/544 ,  H01L23/58

    CPC分类号： H01L22/32 ,  H01L22/34

    摘要： A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

    摘要翻译： 提供了一种测试图案和使用其的CMP控制方法。 测试图案设置在具有主区域和监视区域的半导体衬底的监视区域上。 测试图案包括平面区域和图案区域。 该方法包括设置测试图案的阶梯差和主图案的蚀刻厚度之间的相关性，然后将CMP施加到具有测试图案和主图案的半导体衬底预定时间。 测量测试图案的阶差，并根据相关性确定对应于测试图案的阶差的主图案的蚀刻厚度。 通过将确定的主图案的蚀刻厚度与参考值进行比较来校正抛光时间，并且将修正的抛光时间应用于随后的批次或随后的基板。

    Chemical mechanical polishing slurry
    6.
    发明授权
    Chemical mechanical polishing slurry 有权
    化学机械抛光浆

    公开(公告)号：US06855267B2

    公开(公告)日：2005-02-15

    申请号：US10023948

    申请日：2001-12-21

    申请人： Jae-dong Lee ,  Bo-un Yoon ,  Sang-rok Hah

    发明人： Jae-dong Lee ,  Bo-un Yoon ,  Sang-rok Hah

    IPC分类号： B24B37/00 ,  C09C1/68 ,  C09G1/02 ,  C09K3/14 ,  H01L21/304 ,  H01L21/321 ,  C09K13/00 ,  C09K13/06 ,  H01L21/302

    CPC分类号： C09G1/02 ,  H01L21/3212

    摘要： A polishing slurry including an abrasive, deionized water, a pH controlling agent, and polyethylene imine, can control the removal rates of a silicon oxide layer and a silicon nitride layer which are simultaneously exposed during chemical mechanical polishing (CMP) of a conductive layer. A relative ratio of the removal rate of the silicon oxide layer to that of the silicon nitride layer can be controlled by controlling an amount of the choline derivative.

    摘要翻译： 包括研磨剂，去离子水，pH控制剂和聚乙烯亚胺的抛光浆料可以控制在导电层的化学机械抛光（CMP）期间同时暴露的氧化硅层和氮化硅层的去除速率。 可以通过控制胆碱衍生物的量来控制氧化硅层与氮化硅层的去除速率的相对比例。

    CMOS image sensor and method for fabricating the same
    7.
    发明授权
    CMOS image sensor and method for fabricating the same 失效

    公开(公告)号：US06518115B2

    公开(公告)日：2003-02-11

    申请号：US09891212

    申请日：2001-06-26

    申请人： Jae-Dong Lee ,  Sang-Joo Lee

    发明人： Jae-Dong Lee ,  Sang-Joo Lee

    IPC分类号： H01L218238

    CPC分类号： H01L27/14609 ,  H01L27/14643

    摘要： A CMOS image sensor containing a plurality of unit pixels, each unit pixel having a light sensing region and a peripheral circuit region, includes: a semiconductor substrate of a first conductive type; a transistor formed on the peripheral circuit region of the semiconductor substrate, wherein the transistor has a gate oxide layer and a gate electrode formed on the gate oxide layer; spacers formed on sidewalls of the gate oxide layer and the gate electrode, wherein one spacer are formed on the light sensing region; a first doping region of a second conductive type formed on the light sensing region, wherein the first doping region is extended to an edge of the gate electrode; and a second doping region of the first conductive type formed on the first doping region, wherein the second doping region is extended to an edge of a spacer formed on the light sensing region.

    Image sensor having blooming effect preventing circuitry
    8.
    发明授权
    Image sensor having blooming effect preventing circuitry 有权
    具有防溢出效果的电路的图像传感器

    公开(公告)号：US06410901B1

    公开(公告)日：2002-06-25

    申请号：US09693185

    申请日：2000-10-19

    申请人： Jae-Dong Lee ,  Ju-Il Lee

    发明人： Jae-Dong Lee ,  Ju-Il Lee

    IPC分类号： H01L2700

    CPC分类号： H04N5/3594 ,  H01L27/14654

    摘要： An image sensor includes a plurality of unit pixels for sensing a light beam to generate an image data. Each unit pixel includes a light sensing element for sensing a light beam incident thereto and generating photoelectric charges, a transferring unit for transferring the photoelectric charges to a sensing node, a first resetting unit for making a fully depleted region within the light sensing element and resetting the sensing node by providing a power supply voltage to the sensing node, and a second resetting unit for transferring excess charges generated in the light sensing element to a power line when the sensing node is reset.

    摘要翻译： 图像传感器包括用于感测光束以生成图像数据的多个单位像素。 每个单位像素包括用于感测入射到其上的光束并产生光电电荷的光感测元件，用于将光电电荷传送到感测节点的转移单元，用于在光感测元件内形成完全耗尽区域的第一复位单元 所述感测节点通过向所述感测节点提供电源电压;以及第二复位单元，用于当所述感测节点被复位时，将在所述感光元件中产生的多余电荷转移到电力线。

    Analog semiconductor device and method of fabricating the same
    9.
    发明授权
    Analog semiconductor device and method of fabricating the same 有权
    模拟半导体器件及其制造方法

    公开(公告)号：US06215142B1

    公开(公告)日：2001-04-10

    申请号：US09217342

    申请日：1998-12-21

    申请人： Jae Dong Lee ,  Myung Hwan Cha

    发明人： Jae Dong Lee ,  Myung Hwan Cha

    IPC分类号： H01L2972

    CPC分类号： H01L27/0629

    摘要： An analog semiconductor device capable of preventing open of interconnection lines and notching due to step between transistor and capacitor regions is disclosed. An analog semiconductor device according to the present invention, includes a semiconductor substrate; a first, a second, and a third isolating layer of trench type formed on the substrate and defining a transistor region and a capacitor region, respectively; a lower electrode of a capacitor formed in the surface of the substrate of the capacitor region; an oxide layer formed under the lower electrode and insulating the lower electrode and the substrate; an gate insulating layer formed on the substrate of the transistor region; an dielectric layer formed on the lower electrode; a gate formed on the gate insulating layer; an upper electrode of the capacitor formed on the dielectric layer.

    摘要翻译： 公开了一种能够防止互连线断开和由于晶体管和电容器区域之间的步骤而引起的开槽的模拟半导体器件。根据本发明的模拟半导体器件包括半导体衬底; 分别形成在衬底上并分别限定晶体管区域和电容器区域的第一，第二和第三沟槽隔离层; 形成在电容器区域的基板的表面中的电容器的下电极; 形成在所述下电极下方并使所述下电极和所述基板绝缘的氧化物层; 形成在晶体管区域的基板上的栅极绝缘层; 形成在下电极上的电介质层; 形成在栅极绝缘层上的栅极; 形成在电介质层上的电容器的上电极。