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1.发明申请Capacitive devices, organic dielectric laminates, multilayer structures incorporating such devices, and methods of making thereof 有权电容器件，有机介电层压板，并入这种器件的多层结构及其制造方法公开(公告)号：US20070006435A1
公开(公告)日：2007-01-11
申请号：US11451763
申请日：2006-06-13
申请人： Sounak Banerji , G. Cox , Karl Dietz
发明人： Sounak Banerji , G. Cox , Karl Dietz
CPC分类号： H05K1/162 , H01L21/4857 , H01L23/49822 , H01L23/49894 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/01087 , H01L2924/15311 , H01L2924/19105 , H01L2924/3011 , H05K3/4602 , H05K3/4626 , H05K3/4688 , H05K2201/0209 , H05K2203/066 , Y10T29/43 , Y10T29/435 , Y10T29/4913 , Y10T29/49147 , Y10T29/49156 , Y10T29/49165
摘要： The present invention relates to methods of forming multilayer structures and the structures themselves. In one embodiment, a method of forming a multilayer structure comprising: providing a dielectric composition comprising: paraelectric filler and polymer wherein said paraelectric filler has a dielectric constant between 50 and 150; applying said dielectric composition to a carrier film thus forming a multilayer film comprising a dielectric layer and carrier film layer; laminating said multilayer film to a circuitized core wherein the dielectric layer of said multilayer film is facing said circuitized core; and removing said carrier film layer from said dielectric layer prior to processing; applying a metallic layer to said dielectric layer wherein said circuitized core, dielectric layer and metallic layer form a planar capacitor; and processing said planar capacitor to form a multilayer structure.
摘要翻译： 本发明涉及形成多层结构和结构本身的方法。 在一个实施方案中，形成多层结构的方法包括：提供电介质组合物，其包括：顺电填料和聚合物，其中所述顺电填料具有介于50和150之间的介电常数; 将所述电介质组合物施加到载体膜上，从而形成包含介电层和载体膜层的多层膜; 将所述多层膜层压到电路化芯，其中所述多层膜的电介质层面向所述电路化芯; 以及在处理之前从所述电介质层去除所述载体膜层; 将金属层施加到所述电介质层，其中所述电路化芯，电介质层和金属层形成平面电容器; 并处理所述平面电容器以形成多层结构。
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公开(公告)号：US20060133057A1
公开(公告)日：2006-06-22
申请号：US11289961
申请日：2005-11-30
申请人： David McGregor , Daniel Amey , Sounak Banerji , William Borland , Karl Dietz , Attiganal Sreeram
发明人： David McGregor , Daniel Amey , Sounak Banerji , William Borland , Karl Dietz , Attiganal Sreeram
IPC分类号： H05K7/06
CPC分类号： H05K1/186 , H05K1/0231 , H05K1/162 , H05K3/4641 , H05K2201/09309 , H05K2201/10636 , Y02P70/611
摘要： The present invention relates to a power core comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.
摘要翻译： 电源核心技术领域本发明涉及一种功率核心，包括：至少一个嵌入式表面贴装技术（SMT）离散芯片电容器层，包括至少一个嵌入式SMT分立片式电容器; 和至少一个平面电容器层压板; 其中至少一个平面电容器层叠体用作低电感路径以向至少一个嵌入式SMT分立片式电容器提供电荷; 并且其中所述嵌入式SMT分立片式电容器与所述平面电容层叠体并联连接。
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公开(公告)号：US2295637A
公开(公告)日：1942-09-15
申请号：US37766741
申请日：1941-02-06
申请人： KARL DIETZ
发明人： KARL DIETZ
CPC分类号： C04B28/105 , C04B28/00 , C04B20/0076 , C04B22/06
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公开(公告)号：US20060138591A1
公开(公告)日：2006-06-29
申请号：US11289994
申请日：2005-11-30
申请人： Daniel Amey , Sounak Banerji , William Borland , Karl Dietz , David McGregor , Attiganal Sreeram
发明人： Daniel Amey , Sounak Banerji , William Borland , Karl Dietz , David McGregor , Attiganal Sreeram
IPC分类号： H01L29/00
CPC分类号： H01L23/66 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L2224/16225 , H01L2224/16235 , H01L2924/00011 , H01L2924/00014 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H01L2924/19105 , H01L2924/3011 , H05K1/162 , H05K3/429 , H05K3/4602 , H05K3/4641 , H05K2201/0355 , H05K2201/09309 , H05K2201/09536 , H05K2201/09763 , H01L2224/0401
摘要： The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said at least one embedded singulated capacitor; and wherein said at least one embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and wherein said power core is interconnected to at least one signal layer.
摘要翻译： 本发明涉及一种包括功率核心的器件，其中所述功率核心包括：至少一个嵌入的单个电容器层，其包含至少一个嵌入式单电容器; 和至少一个平面电容器层压板; 其中所述平面电容器层叠体用作低电感路径以向所述至少一个嵌入式分离电容器提供电荷; 并且其中所述至少一个嵌入式单电容器与所述平面电容器层压体中的至少一个并联连接; 并且其中所述功率核心与至少一个信号层相互连接。
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公开(公告)号：US2425976A
公开(公告)日：1947-08-19
申请号：US38060541
申请日：1941-02-26
申请人： KARL DIETZ
发明人： KARL DIETZ
IPC分类号： C04B28/26
CPC分类号： C04B28/26 , Y02W30/94 , Y10S220/917 , C04B14/06 , C04B18/141 , C04B22/12
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公开(公告)号：US2390198A
公开(公告)日：1945-12-04
申请号：US39489041
申请日：1941-05-23
申请人： HEDWIG VOSS , KARL DIETZ , HEINZ THOMAS
发明人： HEDWIG VOSS , KARL DIETZ , HEINZ THOMAS
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公开(公告)号：US20060158828A1
公开(公告)日：2006-07-20
申请号：US11289884
申请日：2005-11-30
申请人： Daniel Amey , Sounak Banerji , William Borland , David McGregor , Attiganal Sreeram , Karl Dietz
发明人： Daniel Amey , Sounak Banerji , William Borland , David McGregor , Attiganal Sreeram , Karl Dietz
IPC分类号： H01G4/06
CPC分类号： H05K1/162 , H01L2924/0002 , H05K3/4641 , H05K2201/0355 , H05K2201/09309 , H05K2201/09763 , H01L2924/00
摘要： A power core comprising: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded singulated capacitor; and wherein said embedded singulated capacitor is connected in parallel to said planar capacitor laminate.
摘要翻译： 一种功率核心，包括：至少一个嵌入的单个电容器层，其包含至少一个嵌入式单电容器; 和至少一个平面电容器层压板; 其中至少一个平面电容器层叠体用作低电感路径，以向至少一个嵌入的单个电容器提供电荷; 并且其中所述嵌入式单电容器与所述平面电容器层压体并联连接。
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