公开(公告)号：US08466549B2

公开(公告)日：2013-06-18

申请号：US13244133

申请日：2011-09-23

申请人： Kentaro Ochi ,  Akira Mishima ,  Takuro Kanazawa ,  Tetsuo Iijima ,  Katsuo Ishizaka ,  Norio Kido

发明人： Kentaro Ochi ,  Akira Mishima ,  Takuro Kanazawa ,  Tetsuo Iijima ,  Katsuo Ishizaka ,  Norio Kido

IPC分类号： H01L23/34

CPC分类号： H01L23/3107 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/33 ,  H01L25/115 ,  H01L2224/32245 ,  H01L2924/1301 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. The third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.

摘要翻译： 提供了通过使用半导体封装形成的半导体器件。 半导体器件包括在感应导体上相邻布置的两个半导体封装。 两个半导体封装的端子由第三引线连接。 第三引线被布置成基本上平行于感应导体。 接头部分处的引线例如具有弯曲结构，并且第三引线布置成靠近感应导体。

公开(公告)号：US07969000B2

公开(公告)日：2011-06-28

申请号：US12706295

申请日：2010-02-16

申请人： Yukihiro Sato ,  Norio Kido ,  Tatsuhiro Seki ,  Katsuo Ishizaka ,  Ichio Shimizu

发明人： Yukihiro Sato ,  Norio Kido ,  Tatsuhiro Seki ,  Katsuo Ishizaka ,  Ichio Shimizu

IPC分类号： H01L27/092

CPC分类号： H01L23/49575 ,  H01L23/485 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/85447 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011

摘要： A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.

摘要翻译： 具有多个芯片的半导体器件的尺寸减小。 在用于驱动三相电机的HSOP（半导体器件）中，包括pMISFET的第一半导体芯片和包括nMISFET的第二半导体芯片安装在第一突片，第二突片和第三突片的每一个上。 pMISFET和nMISFET的漏极在每个接片上彼此电连接。 因此，可以将六个MISFET中的两个放置在与电机的相位数相对应地分开的三个接片中的每一个上，并且它们可以以紧凑的方式封装在一个中。 结果，可以减少具有多个芯片的用于驱动三相电动机的HSOP的尺寸。

公开(公告)号：US20100315786A1

公开(公告)日：2010-12-16

申请号：US12797317

申请日：2010-06-09

申请人： Kentaro OCHI ,  Akira MISHIMA ,  Takuro KANAZAWA ,  Tetsuo IIJIMA ,  Katsuo ISHIZAKA ,  Norio KIDO

发明人： Kentaro OCHI ,  Akira MISHIMA ,  Takuro KANAZAWA ,  Tetsuo IIJIMA ,  Katsuo ISHIZAKA ,  Norio KIDO

IPC分类号： H05K7/20 ,  H05K7/04

CPC分类号： H01L23/3107 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/33 ,  H01L25/115 ,  H01L2224/32245 ,  H01L2924/1301 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.

摘要翻译： 提供了通过使用半导体封装形成的半导体器件。 半导体器件包括在感应导体上相邻布置的两个半导体封装。 两个半导体封装的端子由第三引线连接。 第三引线被布置成基本上平行于感应导体。 接头部分处的引线例如具有弯曲结构，并且第三引线布置成靠近感应导体。

公开(公告)号：US07692285B2

公开(公告)日：2010-04-06

申请号：US11476868

申请日：2006-06-29

申请人： Yukihiro Sato ,  Norio Kido ,  Tatsuhiro Seki ,  Katsuo Ishizaka ,  Ichio Shimizu

发明人： Yukihiro Sato ,  Norio Kido ,  Tatsuhiro Seki ,  Katsuo Ishizaka ,  Ichio Shimizu

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/485 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/85447 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011

摘要： A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.

摘要翻译： 具有多个芯片的半导体器件的尺寸减小。 在用于驱动三相电机的HSOP（半导体器件）中，包括pMISFET的第一半导体芯片和包括nMISFET的第二半导体芯片安装在第一突片，第二突片和第三突片的每一个上。 pMISFET和nMISFET的漏极在每个接片上彼此电连接。 因此，可以将六个MISFET中的两个放置在与电机的相位数相对应地分开的三个接片中的每一个上，并且它们可以以紧凑的方式封装在一个中。 结果，可以减少具有多个芯片的用于驱动三相电动机的HSOP的尺寸。

公开(公告)号：US20080076238A1

公开(公告)日：2008-03-27

申请号：US11833619

申请日：2007-08-03

申请人： Isao Miyashita ,  Yuji Fujii ,  Hajime Ebara ,  Katsuo Ishizaka ,  Norio Hosoya ,  Hidekazu Okuda

发明人： Isao Miyashita ,  Yuji Fujii ,  Hajime Ebara ,  Katsuo Ishizaka ,  Norio Hosoya ,  Hidekazu Okuda

IPC分类号： H01L21/265

CPC分类号： H01L29/66348 ,  H01L23/49562 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/7397 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00

摘要： Provided is a technology of carrying out activation annealing of n type impurity ions implanted for the formation of a field stop layer (n+ type semiconductor region) and activation annealing of p type impurity ions implanted for the formation of a collector region (p+ type semiconductor region) in separate steps to adjust an activation ratio of the n type impurity ions in the field stop layer to 60% or greater and an activation ratio of the p type impurity ions in the collector region to from 1 to 15%. This makes it possible to form an IGBT having a high breakdown voltage and high-speed switching characteristics. Moreover, use of a film stack made of nickel silicide, titanium, nickel and gold films for a collector electrode makes it possible to provide an ohmic contact with the collector region.

摘要翻译： 提供了为了形成场阻止层（n + SUP型半导体区域）而注入的n型杂质离子进行活化退火的技术，以及用于形成 集电极区域（p + SUP +型半导体区域），以将场致发射层中的n型杂质离子的活化比调节至60％以上，p型杂质的活化率 在集电极区域的离子为1〜15％。 这使得可以形成具有高击穿电压和高速开关特性的IGBT。 此外，使用由硅化镍，钛，镍和金膜构成的用于集电极电极的膜堆叠使得可以与集电极区域提供欧姆接触。

公开(公告)号：US20080012045A1

公开(公告)日：2008-01-17

申请号：US11776393

申请日：2007-07-11

申请人： Akira Muto ,  Ichio Shimizu ,  Tetsuo Iljima ,  Toshiyuki Hata ,  Katsuo Ishizaka

发明人： Akira Muto ,  Ichio Shimizu ,  Tetsuo Iljima ,  Toshiyuki Hata ,  Katsuo Ishizaka

IPC分类号： H01L31/111 ,  H01L21/00

CPC分类号： H01L23/49562 ,  H01L21/565 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device is provided, which is capable of improving mounting flexibility relatively and increasing general versatility, as well as realizing heat radiation characteristics and low on-resistance. Moreover, the semiconductor device is provided, which is capable of improving reliability, performing processing in manufacturing processes easily and reducing manufacturing costs. Also, the semiconductor device capable of decreasing the mounting area is provided. A semiconductor chip in which an IGBT is formed and a semiconductor chip in which a diode is formed are mounted over a die pad. Then, the semiconductor chip and the semiconductor chip are connected by using a clip. The clip is arranged so as not to overlap with bonding pads formed at the semiconductor chip in a flat state. The bonding pads formed at the semiconductor chip are connected to electrodes by using wires.

摘要翻译： 提供了一种半导体器件，其能够相对地提高安装灵活性并增加通用性，并且实现热辐射特性和低导通电阻。 此外，提供了能够提高可靠性，容易地进行制造工艺的处理并降低制造成本的半导体器件。 此外，还提供了能够减小安装面积的半导体器件。 其中形成IGBT的半导体芯片和其中形成有二极管的半导体芯片安装在管芯焊盘上。 然后，使用夹子连接半导体芯片和半导体芯片。 夹子被布置成不与形成在半导体芯片处的平坦状态的接合焊盘重叠。 通过使用导线将形成在半导体芯片上的接合焊盘连接到电极。

公开(公告)号：US08035222B2

公开(公告)日：2011-10-11

申请号：US12968534

申请日：2010-12-15

申请人： Kentaro Ochi ,  Akira Mishima ,  Takuro Kanazawa ,  Tetsuo Iijima ,  Katsuo Ishizaka ,  Norio Kido

发明人： Kentaro Ochi ,  Akira Mishima ,  Takuro Kanazawa ,  Tetsuo Iijima ,  Katsuo Ishizaka ,  Norio Kido

IPC分类号： H01L23/34

CPC分类号： H01L23/3107 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/33 ,  H01L25/115 ,  H01L2224/32245 ,  H01L2924/1301 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.

摘要翻译： 提供了通过使用半导体封装形成的半导体器件。 半导体器件包括在感应导体上相邻布置的两个半导体封装。 两个半导体封装的端子由第三引线连接。 第三引线被布置成基本上平行于感应导体。 接头部分处的引线例如具有弯曲结构，并且第三引线布置成靠近感应导体。

公开(公告)号：US20120012978A1

公开(公告)日：2012-01-19

申请号：US13244133

申请日：2011-09-23

申请人： Kentaro OCHI ,  Akira Mishima ,  Takuro Kanazawa ,  Tetsuo Iijima ,  Katsuo Ishizaka ,  Norio Kido

发明人： Kentaro OCHI ,  Akira Mishima ,  Takuro Kanazawa ,  Tetsuo Iijima ,  Katsuo Ishizaka ,  Norio Kido

IPC分类号： H01L23/48

CPC分类号： H01L23/3107 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/33 ,  H01L25/115 ,  H01L2224/32245 ,  H01L2924/1301 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.

摘要翻译： 提供了通过使用半导体封装形成的半导体器件。 半导体器件包括在感应导体上相邻布置的两个半导体封装。 两个半导体封装的端子由第三引线连接。 第三引线被布置成基本上平行于感应导体。 接头部分处的引线例如具有弯曲结构，并且第三引线布置成靠近感应导体。

公开(公告)号：US07872348B2

公开(公告)日：2011-01-18

申请号：US12797317

申请日：2010-06-09

申请人： Kentaro Ochi ,  Akira Mishima ,  Takuro Kanazawa ,  Tetsuo Iijima ,  Katsuo Ishizaka ,  Norio Kido

发明人： Kentaro Ochi ,  Akira Mishima ,  Takuro Kanazawa ,  Tetsuo Iijima ,  Katsuo Ishizaka ,  Norio Kido

IPC分类号： H01L23/34

CPC分类号： H01L23/3107 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/33 ,  H01L25/115 ,  H01L2224/32245 ,  H01L2924/1301 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.

公开(公告)号：US20100140718A1

公开(公告)日：2010-06-10

申请号：US12706295

申请日：2010-02-16

申请人： Yukihiro Sato ,  Norio Kido ,  Tatsuhiro Seki ,  Katsuo Ishizaka ,  Ichio Shimizu

发明人： Yukihiro Sato ,  Norio Kido ,  Tatsuhiro Seki ,  Katsuo Ishizaka ,  Ichio Shimizu

IPC分类号： H01L27/092

CPC分类号： H01L23/49575 ,  H01L23/485 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/85447 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011

摘要： A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.

摘要翻译： 具有多个芯片的半导体器件的尺寸减小。 在用于驱动三相电机的HSOP（半导体器件）中，包括pMISFET的第一半导体芯片和包括nMISFET的第二半导体芯片安装在第一突片，第二突片和第三突片的每一个上。 pMISFET和nMISFET的漏极在每个接片上彼此电连接。 因此，可以将六个MISFET中的两个放置在与电机的相位数相对应地分开的三个接片中的每一个上，并且它们可以以紧凑的方式封装在一个中。 结果，可以减少具有多个芯片的用于驱动三相电动机的HSOP的尺寸。