公开(公告)号：US08865520B2

公开(公告)日：2014-10-21

申请号：US13216063

申请日：2011-08-23

Applicant: Kuo-Pin Yang ,  Wei-Min Hsiao ,  Cheng-Hui Hung

Inventor： Kuo-Pin Yang ,  Wei-Min Hsiao ,  Cheng-Hui Hung

IPC: H01L21/00 ,  H01L21/20 ,  H01L21/30 ,  H01L21/46 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L21/6835 ,  H01L21/486 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10T156/10

Abstract: The present invention provides a temporary carrier bonding and detaching process. A first surface of a semiconductor wafer is mounted on a first carrier by a first adhesive layer, and a first isolation coating disposed between the first adhesive layer and the first carrier. Then, a second carrier is mounted on the second surface of the semiconductor wafer. The first carrier is detached. Then, the first surface of the semiconductor wafer is mounted on a film frame. The second carrier is detached. The method of the present invention utilizes the second carrier to support and protect the semiconductor wafer, after which the first carrier is detached. Therefore, the semiconductor wafer will not be damaged or broken, thereby improving the yield rate of the semiconductor process. Furthermore, the simplicity of the detaching method for the first carrier allows for improvement in efficiency of the semiconductor process.

Abstract translation: 本发明提供了临时的载体接合和分离工艺。 半导体晶片的第一表面通过第一粘合剂层安装在第一载体上，第一隔离涂层设置在第一粘合层和第一载体之间。 然后，第二载体安装在半导体晶片的第二表面上。 第一个承运人分离。 然后，将半导体晶片的第一表面安装在胶片框架上。 第二个承运人分离。 本发明的方法利用第二载体来支撑和保护半导体晶片，然后分离第一载体。 因此，半导体晶片不会被损坏或破损，从而提高半导体工艺的成品率。 此外，第一载体的分离方法的简单性允许提高半导体工艺的效率。

公开(公告)号：US20110048788A1

公开(公告)日：2011-03-03

申请号：US12583949

申请日：2009-08-28

Applicant: Meng-Jen Wang ,  Kuo-Pin Yang

Inventor： Meng-Jen Wang ,  Kuo-Pin Yang

IPC: H05K1/11 ,  H01B13/00

CPC classification number: H05K3/445 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H05K3/061 ,  H05K2203/0323 ,  H05K2203/1476 ,  H01L2924/00

Abstract: The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method includes the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove that has a side wall and a bottom wall on the first surface of the substrate; (c) forming a conductive metal on the side wall and the bottom wall of the groove so as to form a central groove; (d) forming an annular groove that surrounds the conductive metal on the first surface of the substrate; (e) forming an insulating material in the central groove and the annular groove; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material.

Abstract translation: 本发明涉及一种用于在基板和具有通孔的基板上形成通孔的方法。 该方法包括以下步骤：（a）提供具有第一表面和第二表面的基底; （b）在所述基板的第一表面上形成具有侧壁和底壁的凹槽; （c）在槽的侧壁和底壁上形成导电金属，以形成中心槽; （d）形成围绕所述基板的第一表面上的所述导电金属的环形槽; （e）在所述中央槽和所述环形槽中形成绝缘材料; 和（f）去除衬底的第二表面的一部分以暴露导电金属和绝缘材料。

公开(公告)号：US20100244244A1

公开(公告)日：2010-09-30

申请号：US12726777

申请日：2010-03-18

Applicant: Kuo-Pin Yang

Inventor： Kuo-Pin Yang

IPC: H01L23/498

CPC classification number: H01L23/49816 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/12 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05552

Abstract: The present invention relates to a chip having a bump and a package having the same. The chip includes a chip body, at least one via, a passivation layer, an under ball metal layer and at least one bump. The via penetrates the chip body, and is exposed to a surface of the chip body. The passivation layer is disposed on the surface of the chip body, and the passivation layer has at least one opening. The opening exposes the via. The under ball metal layer is disposed in the opening of the passivation layer, and is connected to the via. The bump is disposed on the under ball metal layer, and includes a first metal layer, a second metal layer and a third metal layer. The first metal layer is disposed on the under ball metal layer. The second metal layer is disposed on the first metal layer. The third metal layer is disposed on the second metal layer. As the bumps can connect two chips, the chip is stackable, and so the density of the product is increased while the size of the product is reduced.

Abstract translation: 本发明涉及具有凸块的芯片和具有该凸块的封装。 芯片包括芯片体，至少一个通孔，钝化层，下部球金属层和至少一个凸块。 通孔穿透芯片体并暴露于芯片体的表面。 钝化层设置在芯片体的表面上，钝化层具有至少一个开口。 开幕式暴露了通道。 下球金属层设置在钝化层的开口中，并连接到通孔。 凸块设置在下球金属层上，并且包括第一金属层，第二金属层和第三金属层。 第一金属层设置在球形金属层的下方。 第二金属层设置在第一金属层上。 第三金属层设置在第二金属层上。 由于凸块可以连接两个芯片，芯片可堆叠，因此产品的密度增加，而产品的尺寸减小。

公开(公告)号：US20080303126A1

公开(公告)日：2008-12-11

申请号：US12018711

申请日：2008-01-23

Applicant: Meng Jen WANG ,  Kuo Pin Yang

Inventor： Meng Jen WANG ,  Kuo Pin Yang

IPC: H01L23/495 ,  H01L21/00

CPC classification number: B81B7/0064 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: A method for manufacturing a microelectromechanical system package is provided. A plurality of cavities is first formed on a surface of a silicon wafer. The surface of the silicon wafer is then bonded to the microelectromechanical system wafer in such a manner that the active areas of the chips on the microelectromechanical system wafer are corresponding to the cavities on the silicon wafer. The structure assembly of the two wafers is finally singulated to form individual microelectromechanical system chips whose active areas are covered by the cavities. In this way, the profile of the microelectromechanical system package may be reduced accordingly.

Abstract translation: 提供了一种用于制造微机电系统封装的方法。 首先在硅晶片的表面上形成多个空腔。 然后将硅晶片的表面以这样的方式结合到微机电系统晶片，使得微机电系统晶片上的芯片的有源区域对应于硅晶片上的空腔。 最终将两个晶片的结构组件分开以形成其有源区域被空腔覆盖的单独的微机电系统芯片。 以这种方式，可以相应地减小微机电系统封装的轮廓。

公开(公告)号：US20080132000A1

公开(公告)日：2008-06-05

申请号：US11871056

申请日：2007-10-11

Applicant: Yu Pin TSAI ,  Kuo Pin Yang ,  Wu Chung Chiang

Inventor： Yu Pin TSAI ,  Kuo Pin Yang ,  Wu Chung Chiang

IPC: H01L21/00

CPC classification number: H01L23/3114 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for marking chip scale packages at the wafer level is provided. First, a positioning step is performed to determine the position of a plurality of semi-finished chip scale packages formed on a wafer. Each of the semi-finished chip scale package includes a plurality of terminals for making external electrical connections and each die has a plurality of bonding pads on an active surface thereof. The bonding pads are electrically connected to the respective terminals wherein a backside surface of the die is exposed from a surface of the respective semi-finished chip scale package. The exposed backside surface of the die is then marked by ink-jet printing. Afterward, the ink marks on the dice are cured. Finally, the wafer is diced to obtain a plurality of separated chip scale packages.

Abstract translation: 提供了一种用于在晶片级标记芯片级封装的方法。 首先，执行定位步骤以确定形成在晶片上的多个半成品芯片级封装的位置。 每个半成品芯片级封装包括用于进行外部电连接的多个端子，并且每个管芯在其有效表面上具有多个焊盘。 接合焊盘电连接到各个端子，其中芯片的背面从相应的半成品芯片尺寸封装的表面露出。 然后通过喷墨打印标记模具的暴露的背面。 之后，骰子上的墨迹被修复。 最后，切割晶片以获得多个分离的芯片级封装。

公开(公告)号：US20070252261A1

公开(公告)日：2007-11-01

申请号：US11612457

申请日：2006-12-18

Applicant: Meng-Jen Wang ,  Kuo-Pin Yang ,  Sheng-Yang Peng ,  Wei-Min Hsiao

Inventor： Meng-Jen Wang ,  Kuo-Pin Yang ,  Sheng-Yang Peng ,  Wei-Min Hsiao

IPC: H01L23/02

CPC classification number: H01L23/04 ,  B81B7/0077 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16151 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to a semiconductor device package, comprising a carrier, a first semiconductor device, a second semiconductor device, a plurality of conductive elements, a pre-mold and a lid. The first semiconductor device is electrically connected to the carrier. The second semiconductor device is disposed above the first semiconductor device. The conductive elements are used for electrically connecting the second semiconductor device and the carrier. The pre-mold and the carrier form an accommodating space for accommodating the first semiconductor device, the second semiconductor device and the conductive elements. The lid is adhered to the pre-mold for covering the opening of the pre-mold. As a result, the pre-mold is formed by molding, the manufacture process of the present invention is simpler than that of the conventional semiconductor device package.

Abstract translation: 本发明涉及一种半导体器件封装，包括载体，第一半导体器件，第二半导体器件，多个导电元件，预模具和盖子。 第一半导体器件电连接到载体。 第二半导体器件设置在第一半导体器件的上方。 导电元件用于电连接第二半导体器件和载体。 预模具和载体形成用于容纳第一半导体器件，第二半导体器件和导电元件的容纳空间。 盖子粘附到预模具以覆盖预模具的开口。 结果，通过模制形成预模具，本发明的制造工艺比传统的半导体器件封装简单。

公开(公告)号：US20060255253A1

公开(公告)日：2006-11-16

申请号：US11287269

申请日：2005-11-28

Applicant: Wei-Min Hsiao ,  Kuo-Pin Yang

Inventor： Wei-Min Hsiao ,  Kuo-Pin Yang

IPC: H01J5/02

CPC classification number: H01L27/14618 ,  H01L27/14683 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/16195 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method and package for packaging an image sensor die utilizes a substrate having a concave space and an opening to connect the image sensor die with the substrate by SMT method. This method can reduce the manufacturing process of packaging the image sensor. The packaging method comprises providing a wafer having a plurality of image sensors, sawing the wafer to form a plurality of dies with a single image sensor, electrically connecting the die having the image sensor with a substrate, the substrate comprising a concave space and an opening, a plurality of solder pads disposed in the concave space for electrically connecting the die having an image sensor, and a plurality of input/output solder pads on the same side of the substrate for connecting to an external element, and filling a transparent adhesive into the opening of the substrate.

Abstract translation: 用于封装图像传感器芯片的方法和封装利用具有凹形空间和开口的基板，通过SMT方法将图像传感器裸片与基板连接。 这种方法可以减少包装图像传感器的制造过程。 包装方法包括提供具有多个图像传感器的晶片，锯切晶片以形成具有单个图像传感器的多个管芯，将具有图像传感器的管芯与基板电连接，该基板包括凹形空间和开口 设置在所述凹形空间中的多个焊盘，用于电连接具有图像传感器的管芯，以及在所述衬底的同一侧上的多个输入/输出焊盘，用于连接到外部元件，并且将透明粘合剂填充到 基板的开口。

公开(公告)号：US07105424B2

公开(公告)日：2006-09-12

申请号：US10983619

申请日：2004-11-09

Applicant: Yu-Pen Tsai ,  Kuo-Pin Yang ,  Wu-Chung Chiang

Inventor： Yu-Pen Tsai ,  Kuo-Pin Yang ,  Wu-Chung Chiang

IPC: H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/563 ,  H01L24/27 ,  H01L24/29 ,  H01L2221/6834 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method for forming an underfill layer on a bumped wafer is disclosed. A film is provided wherein the film includes a base layer, a removable layer and the underfill layer. The film is disposed on a bump wafer and then pressing the film under heating is performed to have the bumps of the wafer embedded in the underfill layer. Then, the removable layer with base film attached thereto is removed, so the underfill layer well encloses the bumps of the wafer and is easily separated from the base film layer and the removable layer without damaging the bumps formed on the wafer.

Abstract translation: 公开了一种在凸起晶片上形成底部填充层的方法。 提供了一种薄膜，其中薄膜包括基底层，可去除层和底部填充层。 将膜设置在凸块晶片上，然后在加热下按压膜以使晶片的凸块嵌入底部填充层中。 然后，除去附着有底膜的可移除层，因此底部填充层良好地包围晶片的凸块，并且容易地从基膜层和可移除层分离，而不损坏在晶片上形成的凸块。

公开(公告)号：US06150730A

公开(公告)日：2000-11-21

申请号：US349231

申请日：1999-07-08

Applicant: Chih-Ming Chung ,  Kuo-Pin Yang ,  Jen-Kuang Fang ,  Su Tao

Inventor： Chih-Ming Chung ,  Kuo-Pin Yang ,  Jen-Kuang Fang ,  Su Tao

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/4951 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/50 ,  H01L2924/14

Abstract: A chip-scale semiconductor package mainly includes a semiconductor chip, a substrate and a package body. Said chip is attached onto said substrate by an adhesive layer. Said chip has a plurality of bonding pads formed thereon. Said adhesive layer has an aperture corresponding to the bonding pads of said chip such that the bonding pads can be exposed within an aperture. Said substrate has several through-holes respectively corresponding to the bonding pads of said chip and parts of the area around the edge of said chip for dispensing of encapsulant after the soldering of leads of said substrate to the bonding pads of said chip. The encapsulant dispensed into the through-holes can flow from the surface of said chip to the edge thereof. Said package body has one portion provided within the through-hole of said substrate and another portion provided around the edge of said chip whereby encapsulation process is accomplished without having to turn the whole semiconductor package device.

Abstract translation: 芯片级半导体封装主要包括半导体芯片，基板和封装体。 所述芯片通过粘合剂层附着在所述基板上。 所述芯片具有形成在其上的多个接合焊盘。 所述粘合剂层具有对应于所述芯片的焊盘的孔，使得焊盘可以暴露在孔内。 所述衬底具有分别对应于所述芯片的焊盘和所述芯片的边缘周围区域的部分的多个通孔，用于在将所述衬底的引线焊接到所述芯片的焊盘之后分配密封剂。 分配到通孔中的密封剂可以从所述芯片的表面流动到其边缘。 所述封装体具有设置在所述基板的通孔内的一部分和设置在所述芯片的边缘周围的另一部分，从而实现封装处理而不必转动整个半导体封装器件。

公开(公告)号：US08471156B2

公开(公告)日：2013-06-25

申请号：US12583949

申请日：2009-08-28

Applicant: Meng-Jen Wang ,  Kuo-Pin Yang

Inventor： Meng-Jen Wang ,  Kuo-Pin Yang

IPC: H05K1/11

CPC classification number: H05K3/445 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H05K3/061 ,  H05K2203/0323 ,  H05K2203/1476 ,  H01L2924/00

Abstract: The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method includes the following steps: (a) providing a substrate; (b) forming a groove on a first surface of the substrate; (c) forming a conductive metal on the groove so as to form a central groove; (d) forming an annular groove that surrounds the conductive metal; (e) forming an insulating material in the central groove and the annular; groove; and (f) removing part of the substrate to expose the conductive metal and the insulating material.

Abstract translation: 本发明涉及一种用于在基板和具有通孔的基板上形成通孔的方法。 该方法包括以下步骤：（a）提供衬底; （b）在所述基板的第一表面上形成凹槽; （c）在槽上形成导电金属以形成中心槽; （d）形成围绕所述导电金属的环形槽; （e）在中央槽和环形中形成绝缘材料; 槽; 和（f）去除衬底的一部分以暴露导电金属和绝缘材料。