公开(公告)号：US06396153B2

公开(公告)日：2002-05-28

申请号：US09768598

申请日：2001-01-25

申请人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

发明人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

IPC分类号： H01L2348

CPC分类号： H01L24/48 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/24227 ,  H01L2224/4824 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.

摘要翻译： 一种用于封装至少一个电路芯片的方法包括：提供包括具有第一侧和第二侧的绝缘材料的互连层，在第二侧的第二侧金属化部分上而不是在第二侧非金属化部分上图案化的初始金属化 第二侧，至少一个从第一侧延伸到第二侧金属化部分之一的衬底通孔;以及至少一个芯片通孔，其从第一侧延伸到第二侧非金属化部分之一; 将所述至少一个电路芯片定位在所述第二侧上，所述至少一个电路芯片的至少一个芯片焊盘与所述至少一个芯片通孔对准; 以及在所述互连层的第一侧和所述通孔的选定部分上图案化连接金属化，以便延伸到所述至少一个第二侧金属化部分和所述至少一个芯片焊盘。 在相关实施例中，通孔被预先金属化并且通过导电粘合剂耦合到电路芯片的芯片焊盘。 薄膜无源元件和多层互连可另外包含在封装中。

公开(公告)号：US6040226A

公开(公告)日：2000-03-21

申请号：US177908

申请日：1998-10-23

申请人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

发明人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

IPC分类号： H01L21/20

CPC分类号： H01L21/20

摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.

摘要翻译： 提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。 电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。 薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。 可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。

公开(公告)号：US06790703B2

公开(公告)日：2004-09-14

申请号：US10199296

申请日：2002-07-22

申请人： Richard Joseph Saia ,  Kevin Matthew Durocher ,  James Wilson Rose ,  Leonard Richard Douglas

发明人： Richard Joseph Saia ,  Kevin Matthew Durocher ,  James Wilson Rose ,  Leonard Richard Douglas

IPC分类号： H01L2158

CPC分类号： H01L24/76 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1423 ,  Y10T29/49131 ,  H01L2924/00

摘要： A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using “adaptive lithography”. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost. The method is compatible with the projected designs of the next generation die which will have bond pads on the order of 40um in size.

摘要翻译： 描述了用于精确对准（模具与柔性基板上的互连金属如聚酰亚胺柔性）的方法和工艺顺序，首先在柔性基板的底表面上的金属层中对通孔形成用掩模进行图案化， 然后将附着的粘合剂施加到柔性基板的顶侧，芯片上的接合焊盘以高精度局部地适应性地与柔性上的图案化金属通孔掩模对准，然后通过等离子体蚀刻 或准分子激光烧蚀通过柔性基板上的现有对准的金属掩模，然后沉积，图案化和蚀刻互连金属。作为该过程的结果，柔性金属互连图案不需要针对每个管芯错位进行定制， 适应光刻“，低成本商业光刻设备可用于加工，减少资本设备和加工成本，该方法与p 下一代模具的抛光设计将具有大小为40um的接合垫。

公开(公告)号：US06410356B1

公开(公告)日：2002-06-25

申请号：US09520751

申请日：2000-03-07

申请人： Robert John Wojnarowski ,  Ernest Wayne Balch ,  Leonard Richard Douglas

发明人： Robert John Wojnarowski ,  Ernest Wayne Balch ,  Leonard Richard Douglas

IPC分类号： H01L2166

CPC分类号： H01L22/20 ,  H01L23/34 ,  H01L2224/92144 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/00

摘要： A method for interconnecting high-temperature silicon carbide (SiC) devices enables such high-temperature devices to be used in fabricating electronic circuits of significant scale. This method comprises empirically measuring operational characteristics of a plurality of the devices to be interconnected, the operational characteristics comprising devices which are measured to be non-working and devices which are measured to be working; characterizing the operational characteristics in an operational characteristics map; designing interconnection paths between and among the devices that are characterized to be working by the operational characteristics map; and excluding from the interconnection paths, devices that are characterized to be non-working by the operational characteristics map. A preferred embodiment of this method further includes disposing a temporary polymer layer over the devices; forming via holes through the temporary polymer layer, to bonding pads of the devices; applying a current-balancing resistive metal over the temporary polymer layer; establishing connections between the current-balancing resistive metal and the bonding pads; designing the interconnection paths between and among the working devices by patterning the current-balancing resistive metal based on the operational characteristics map; and removing the temporary polymer layer.

摘要翻译： 用于互连高温碳化硅（SiC）器件的方法使得这种高温器件能够用于制造具有显着规模的电子电路。 该方法包括经验地测量待互连的多个设备的操作特性，操作特性包括被测量为不工作的设备和被测量为工作的设备; 表征操作特征图中的操作特性; 设计特征在于通过操作特征图工作的设备之间的互连路径; 并且从互连路径中排除特征在于通过操作特性图不工作的设备。 该方法的优选实施例还包括在器件上设置临时聚合物层; 通过所述临时聚合物层形成通孔到所述装置的焊盘; 在临时聚合物层上施加电流平衡电阻金属; 建立电流平衡电阻金属和焊盘之间的连接; 通过基于操作特性图构图电流平衡电阻金属来设计工作装置之间和之间的互连路径; 并除去临时聚合物层。

公开(公告)号：US06284564B1

公开(公告)日：2001-09-04

申请号：US09399461

申请日：1999-09-20

申请人： Ernest Wayne Balch ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

发明人： Ernest Wayne Balch ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

IPC分类号： H01L2144

CPC分类号： H01L24/76 ,  H01L21/67138 ,  H01L24/24 ,  H01L24/82 ,  H01L24/86 ,  H01L2224/24225 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01058

摘要： A method according to an aspect of the invention, for interconnecting electrical contacts or electrodes (230be) of semiconductor chips (230a, 230b, 230c) in an HDI context, includes the step of applying laser energy to make a pattern of apertures through a dielectric film which corresponds to the ideal locations of electrodes of semiconductor chips properly placed on the film. This may be accomplished, in one mode of the method, by procuring an optical mask (20) defining an ideal pattern of electrodes of semiconductor chips properly aligned in an HDI structure. This mask may be sufficiently large to cover a plurality of HDI circuits being made on a substrate, or it may cover only one such HDI circuit. Laser energy (30) is applied to a dielectric film (10; 10, 17) through apertures or transparent regions (22) of the mask, to thereby make the ideal pattern of holes in the film. Semiconductor chips (230a, 230b, 230c) are mounted to a first side (10ls, 17ls) of the dielectric film, as by means of adhesive, with the electrodes (230be) in registry with the corresponding ones of the holes (22). This has the effect of mounting the semiconductor chips (230a, 230b, 230c) in their ideal locations. Electrically conductive material (310), such as metallization, is applied to a second side (10us) of the film (10) and to at least the sides of the holes (42a, 42b), so as to interconnect the electrodes (230be) with an interconnect pattern (320) of the electrically conductive material (310).

摘要翻译： 根据本发明的一个方面，用于使HDI环境中的半导体芯片（230a，230b，230c）的电接触或电极（230be）互连的方法包括施加激光能量以通过电介质形成孔径图案的步骤 膜对应于半导体芯片的适当放置在膜上的电极的理想位置。 这可以在该方法的一种模式中通过采购限定在HDI结构中正确对准的半导体芯片的理想电极图案的光学掩模（20）来实现。 该掩模可能足够大以覆盖在衬底上制造的多个HDI电路，或者它可以仅覆盖一个这样的HDI电路。 通过掩模的孔或透明区域（22）将激光能量（30）施加到电介质膜（10; 10,17）上，从而在膜中形成理想的孔图案。 半导体芯片（230a，230b，230c）通过粘合剂安装到电介质膜的第一侧（10l，17ls）上，电极（230be）与对应的孔（22）对准。 这具有将半导体芯片（230a，230b，230c）安装在其理想位置的效果。 诸如金属化的导电材料（310）被施加到膜（10）的第二侧（10us）并且至少在孔（42a，42b）的侧面上，以将电极（230be） 具有导电材料（310）的互连图案（320）。

公开(公告)号：US07146081B2

公开(公告)日：2006-12-05

申请号：US11178657

申请日：2005-07-08

申请人： Ernest Wayne Balch ,  Leonard Richard Douglas ,  Min-Yi Shih

发明人： Ernest Wayne Balch ,  Leonard Richard Douglas ,  Min-Yi Shih

IPC分类号： G02B6/26 ,  G02B6/02

CPC分类号： G02B6/1228 ,  G02B6/12004 ,  G02B6/138 ,  G02B6/4228 ,  G02B6/43

摘要： A method for adaptively fabricating a waveguide comprises: measuring misplacement of a photonic device relative to a substrate; generating computer readable instructions for using a plurality of graphics primitives to form the waveguide; and photocomposing the waveguide on the substrate in accordance with the computer readable instructions. A reticle comprises a plurality of graphics primitives with at least one of the plurality of graphics primitives comprising a tapered end. A waveguide comprises a plurality of waveguide segments with each of the plurality of waveguide segments comprising a tapered end and being adjacent to at least one other of the plurality of waveguide segments.

摘要翻译： 用于自适应地制造波导的方法包括：测量光子器件相对于衬底的错位; 生成用于使用多个图形基元形成所述波导的计算机可读指令; 并根据计算机可读指令将基片上的波导照相。 标线板包括多个图形基元，其中所述多个图形基元中的至少一个包括渐缩端。 波导包括多个波导段，其中多个波导段中的每一个包括锥形端并与多个波导区段中的至少另一个相邻。

公开(公告)号：US06242282B1

公开(公告)日：2001-06-05

申请号：US09411101

申请日：1999-10-04

申请人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

发明人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

IPC分类号： H01L2144

CPC分类号： H01L24/48 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/24227 ,  H01L2224/4824 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.

公开(公告)号：US5872040A

公开(公告)日：1999-02-16

申请号：US862994

申请日：1997-05-27

申请人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

发明人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

IPC分类号： H01C17/12 ,  H01C17/24 ,  H01G4/06 ,  H01G4/08 ,  H05K1/16 ,  H01L21/20

CPC分类号： H01C17/24 ,  H01C17/12 ,  H01C17/2416 ,  H01G4/06 ,  H01G4/08 ,  H05K1/167 ,  Y10S148/136

摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.

摘要翻译： 提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。 电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。 薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。 可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。

公开(公告)号：US5683928A

公开(公告)日：1997-11-04

申请号：US349278

申请日：1994-12-05

申请人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

发明人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

IPC分类号： H01C17/12 ,  H01C17/24 ,  H01G4/06 ,  H01G4/08 ,  H05K1/16 ,  H01L21/70

CPC分类号： H01C17/24 ,  H01C17/12 ,  H01C17/2416 ,  H01G4/06 ,  H01G4/08 ,  H05K1/167 ,  Y10S148/136

摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.

摘要翻译： 提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。 电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。 薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。 可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。

公开(公告)号：US06957007B2

公开(公告)日：2005-10-18

申请号：US10064581

申请日：2002-07-29

申请人： Ernest Wayne Balch ,  Leonard Richard Douglas ,  Min-Yi Shih

发明人： Ernest Wayne Balch ,  Leonard Richard Douglas ,  Min-Yi Shih

IPC分类号： G02B6/12 ,  G02B6/122 ,  G02B6/13 ,  G02B6/138 ,  G02B6/42 ,  G02B6/43 ,  G02B6/00 ,  G03C5/00 ,  G06F19/00

CPC分类号： G02B6/1228 ,  G02B6/12004 ,  G02B6/138 ,  G02B6/4228 ,  G02B6/43

摘要： A method for adaptively fabricating a waveguide comprises: measuring misplacement of a photonic device relative to a substrate; generating computer readable instructions for using a plurality of graphics primitives to form the waveguide; and photocomposing the waveguide on the substrate in accordance with the computer readable instructions. A reticle comprises a plurality of graphics primitives with at least one of the plurality of graphics primitives comprising a tapered end. A waveguide comprises a plurality of waveguide segments with each of the plurality of waveguide segments comprising a tapered end and being adjacent to at least one other of the plurality of waveguide segments.

摘要翻译： 用于自适应地制造波导的方法包括：测量光子器件相对于衬底的错位; 生成用于使用多个图形基元形成所述波导的计算机可读指令; 并根据计算机可读指令将基片上的波导照相。 标线板包括多个图形基元，其中所述多个图形基元中的至少一个包括渐缩端。 波导包括多个波导段，其中多个波导段中的每一个包括锥形端并与多个波导区段中的至少另一个相邻。