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公开(公告)号：US6040226A
公开(公告)日：2000-03-21
申请号：US177908
申请日：1998-10-23
申请人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
发明人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
IPC分类号： H01L21/20
CPC分类号： H01L21/20
摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.
摘要翻译： 提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。 电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。 薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。 可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。
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公开(公告)号：US5872040A
公开(公告)日：1999-02-16
申请号：US862994
申请日：1997-05-27
申请人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
发明人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
CPC分类号： H01C17/24 , H01C17/12 , H01C17/2416 , H01G4/06 , H01G4/08 , H05K1/167 , Y10S148/136
摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.
摘要翻译： 提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。 电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。 薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。 可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。
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公开(公告)号：US5683928A
公开(公告)日：1997-11-04
申请号：US349278
申请日：1994-12-05
申请人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
发明人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
CPC分类号： H01C17/24 , H01C17/12 , H01C17/2416 , H01G4/06 , H01G4/08 , H05K1/167 , Y10S148/136
摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.
摘要翻译： 提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。 电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。 薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。 可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。
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公开(公告)号：US5849623A
公开(公告)日：1998-12-15
申请号：US862672
申请日：1997-05-23
IPC分类号： H01C1/032 , H01C7/00 , H01C17/075 , H01L23/538 , H05K1/02 , H05K1/16 , H05K3/38 , H01L21/20
CPC分类号： H05K1/167 , H01C1/032 , H01C17/075 , H01C7/006 , H01L2224/73204 , H01L2224/82039 , H01L23/5389 , H01L2924/01077 , H05K1/0268 , H05K2201/0317 , H05K2203/0361 , H05K2203/171 , H05K3/388 , Y10S148/136 , Y10T29/49101
摘要： A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.
摘要翻译： 一种用于制造薄膜电阻器的方法包括在介电层上施加氮化钽层，在氮化钽层上施加金属化层，以及使金属化层的第一部分与金属化层的第二部分分开， 金属化层，并且第一和第二部分至少部分地位于氮化钽层上。 在一个实施例中，在图案化金属化层之后，确定金属化层的第一和第二部分之间的电阻值并将其与预定电阻值进行比较，并且修剪第一和第二部分中的至少一个以获得改良电阻 第一和第二部分之间的值比所确定的电阻值更接近于预定电阻值。
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公开(公告)号：US5675310A
公开(公告)日：1997-10-07
申请号：US349228
申请日：1994-12-05
IPC分类号： H01C1/032 , H01C7/00 , H01C17/075 , H01L23/538 , H05K1/02 , H05K1/16 , H05K3/38 , H01C1/012 , H01L27/00
CPC分类号： H05K1/167 , H01C1/032 , H01C17/075 , H01C7/006 , H01L2224/73204 , H01L2224/82039 , H01L23/5389 , H01L2924/01077 , H05K1/0268 , H05K2201/0317 , H05K2203/0361 , H05K2203/171 , H05K3/388 , Y10S148/136 , Y10T29/49101
摘要： A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.
摘要翻译： 一种用于制造薄膜电阻器的方法包括在介电层上施加氮化钽层，在氮化钽层上施加金属化层，以及使金属化层的第一部分与金属化层的第二部分分开， 金属化层，并且第一和第二部分至少部分地位于氮化钽层上。 在一个实施例中，在图案化金属化层之后，确定金属化层的第一和第二部分之间的电阻值并将其与预定电阻值进行比较，并且修剪第一和第二部分中的至少一个以获得改良电阻 第一和第二部分之间的值比所确定的电阻值更接近于预定电阻值。
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6.发明授权Method for making multichip module substrates by encapsulating electrical conductors and filling gaps 失效通过封装电导体和填充间隙来制造多芯片模块基板的方法公开(公告)号：US06602739B1
公开(公告)日：2003-08-05
申请号：US10101231
申请日：2002-03-19
申请人： James Wilson Rose , Thomas Bert Gorczyca , Christopher James Kapusta , Ernest Wayne Balch , Kevin Matthew Durocher
发明人： James Wilson Rose , Thomas Bert Gorczyca , Christopher James Kapusta , Ernest Wayne Balch , Kevin Matthew Durocher
IPC分类号： H01L2144
CPC分类号： H01L24/76 , H01L21/4857 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/81 , H01L24/82 , H01L2224/04105 , H01L2224/73267 , H01L2224/81801 , H01L2224/82039 , H01L2224/92144 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/14 , H01L2924/3025 , H05K1/185
摘要： A method for making a multichip “HDI” module includes the step of making a substrate for supporting the semiconductor or solid-state chips (or other components) by applying electrical conductor in a pattern to a first dielectric sheet, and applying encapsulating material to the electrical conductor. Apertures are made in the first dielectric sheet and encapsulant at locations at which the chips (or other components) are to be located. The components are affixed to a second dielectric sheet at locations registered with the apertures in the first sheet, and the sheets are juxtaposed with the chips extending into the apertures. This results in the formation of gaps between the components and the edges of the apertures, which gaps are then filled with hardenable or curable material. Electrical connection is made to the pads of the chips by means of a multilayer structure of dielectric sheets with conductor patterns, interconnected by means of plated-through vias.
摘要翻译： 制造多芯片“HDI”模块的方法包括以下步骤：通过将图案中的电导体施加到第一电介质片上，并且将封装材料施加到第一电介质片上，制备用于支撑半导体或固态芯片（或其它部件）的基板 电导体。 在第一电介质片和密封剂中在芯片（或其他部件）所在的位置处形成孔。 这些部件在与第一片中的孔对准的位置处固定到第二电介质片，并且片材与延伸到孔中的芯片并置。 这导致在部件和孔的边缘之间形成间隙，然后用可硬化或可固化材料填充该间隙。 通过具有通过电镀通孔互连的导体图案的介电片的多层结构对芯片的焊盘进行电连接。
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公开(公告)号：US06417062B1
公开(公告)日：2002-07-09
申请号：US09562194
申请日：2000-05-01
IPC分类号： H01L2120
CPC分类号： H01L28/24 , C23C18/1216 , C23C18/14 , H01L21/288 , H01L21/31683 , H01L21/76888 , H01L28/60 , H05K1/167
摘要： A method of forming a ruthenium dioxide film for such purposes as the fabrication of stable thin-film resistors for microcircuits. The method generally entails forming an inorganic ruthenium-based film on a substrate, and then thermally decomposing at least a portion of the ruthenium-based film by exposure to a high-intensity beam of radiation, preferably visible light, to yield a ruthenium dioxide film on the substrate. Particular ruthenium-based precursors useful for forming the ruthenium-based film include ruthenium (III) chloride (RuCl3.nH2O) and ruthenium (III) nitrosyl nitrate. The method does not require a thermal treatment that heats the bulk of the substrate on which the ruthenium dioxide film is formed, and is therefore suitable for non-ceramic substrate materials, e.g., polymers such as those used as printed circuit boards (PCBs) and flexible circuits.
摘要翻译： 形成用于微电路的稳定薄膜电阻器的制造的目的的二氧化钌膜的方法。 该方法通常需要在基板上形成无机钌基膜，然后通过暴露于高强度辐射束（优选可见光）来热分解钌基膜的至少一部分，以产生二氧化钌膜 在基板上。 用于形成钌基膜的特定的基于钌的前体包括氯化钌（III）（RuCl 3·nH 2 O）和硝酸亚硝基硝酸钌（III）。 该方法不需要加热其上形成有二氧化钌膜的基底的主体的热处理，因此适用于非陶瓷基底材料，例如聚合物，例如用作印刷电路板（PCB）的聚合物和 柔性电路。
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公开(公告)号：US5897728A
公开(公告)日：1999-04-27
申请号：US759691
申请日：1991-09-06
申请人： Herbert Stanley Cole , James Wilson Rose , Robert John Wojnarowski , Charles William Eichelberger
发明人： Herbert Stanley Cole , James Wilson Rose , Robert John Wojnarowski , Charles William Eichelberger
IPC分类号： G01R31/30 , G01R1/04 , G01R31/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L23/538 , H01L23/58 , B32B32/00
CPC分类号： G01R1/04 , G01R31/2863 , H01L22/32 , H01L23/5389 , H01L24/05 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/85 , H01L2224/04042 , H01L2224/05599 , H01L2224/05624 , H01L2224/24227 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48137 , H01L2224/4823 , H01L2224/48465 , H01L2224/48471 , H01L2224/73265 , H01L2224/73267 , H01L2224/82039 , H01L2224/85205 , H01L24/45 , H01L2924/00014 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15312 , H01L2924/15787 , H01L2924/30105
摘要： For fully testing and burning-in an integrated circuit chip before it is incorporated into a high density interconnect or other standard hybrid bare chip circuit, a temporary test substrate having pins extending therethrough holds the chip within a cavity. Chip pads are electrically connected with the pins to create a package that can be tested using commercially available testing and burn-in devices. After testing, the chip is retrieved from the test structure undamaged. In using HDI techniques to interconnect the chip with the pins, metal-filled vias in a polymer layer overlying the temporary test substrate electrically connect the chip to the pins through a metal interconnect pattern on the polymer layer. In another embodiment, the chip is interconnected with the pins through wire bonds. Metal-filled vias pass through an insulative coating on the chip and make electrical contact with the chip pad. A temporary buffer pad connected to a respective via and offset from the chip pad connected to that via comprises a wire-bonding site.
摘要翻译： 为了在将集成电路芯片并入高密度互连或其他标准混合裸芯片电路之前对其进行完全测试和烧录，具有延伸穿过的引脚的临时测试基板将芯片保持在空腔内。 芯片焊盘与引脚电连接以产生可以使用市售测试和老化设备进行测试的封装。 测试后，芯片从测试结构中检索到无损坏。 在使用HDI技术将芯片与引脚互连时，覆盖临时测试基板的聚合物层中的金属填充的通孔通过聚合物层上的金属互连图案将芯片电连接到引脚。 在另一个实施例中，芯片通过引线键与引脚互连。 金属填充的通孔穿过芯片上的绝缘涂层，并与芯片焊盘电接触。 连接到相应通孔并与连接到该通孔的芯片焊盘偏移的临时缓冲垫包括引线接合部位。
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公开(公告)号：US06790703B2
公开(公告)日：2004-09-14
申请号：US10199296
申请日：2002-07-22
IPC分类号： H01L2158
CPC分类号： H01L24/76 , H01L23/5389 , H01L24/19 , H01L24/82 , H01L2223/54426 , H01L2224/04105 , H01L2224/32225 , H01L2224/8314 , H01L2224/83192 , H01L2224/92144 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/01087 , H01L2924/12042 , H01L2924/14 , H01L2924/1423 , Y10T29/49131 , H01L2924/00
摘要： A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using “adaptive lithography”. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost. The method is compatible with the projected designs of the next generation die which will have bond pads on the order of 40um in size.
摘要翻译： 描述了用于精确对准（模具与柔性基板上的互连金属如聚酰亚胺柔性）的方法和工艺顺序，首先在柔性基板的底表面上的金属层中对通孔形成用掩模进行图案化， 然后将附着的粘合剂施加到柔性基板的顶侧，芯片上的接合焊盘以高精度局部地适应性地与柔性上的图案化金属通孔掩模对准，然后通过等离子体蚀刻 或准分子激光烧蚀通过柔性基板上的现有对准的金属掩模，然后沉积，图案化和蚀刻互连金属。作为该过程的结果，柔性金属互连图案不需要针对每个管芯错位进行定制， 适应光刻“，低成本商业光刻设备可用于加工，减少资本设备和加工成本，该方法与p 下一代模具的抛光设计将具有大小为40um的接合垫。
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公开(公告)号：US06475877B1
公开(公告)日：2002-11-05
申请号：US09469749
申请日：1999-12-22
IPC分类号： H01L21301
CPC分类号： H01L24/76 , H01L23/5389 , H01L24/19 , H01L24/82 , H01L2223/54426 , H01L2224/04105 , H01L2224/32225 , H01L2224/8314 , H01L2224/83192 , H01L2224/92144 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/01087 , H01L2924/12042 , H01L2924/14 , H01L2924/1423 , Y10T29/49131 , H01L2924/00
摘要： A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using “adaptive lithography”. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost. The method is compatible with the projected designs of the next generation die which will have bond pads on the order of 40 um in size.
摘要翻译： 描述了用于精确对准（模具与柔性基板上的互连金属如聚酰亚胺柔性）的方法和工艺顺序，首先在柔性基板的底表面上的金属层中对通孔形成用掩模进行图案化， 然后将附着的粘合剂施加到柔性基板的顶侧，芯片上的接合焊盘以高精度局部地适应性地与柔性上的图案化金属通孔掩模对准，然后通过等离子体蚀刻 或准分子激光烧蚀通过柔性基板上的现有对准的金属掩模，然后沉积，图案化和蚀刻互连金属。作为该过程的结果，柔性金属互连图案不需要针对每个管芯错位进行定制， 适应光刻“，低成本商业光刻设备可用于加工，减少资本设备和加工成本，该方法与p 下一代芯片的焊接设计将具有大小为40um的接合焊盘。
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