公开(公告)号：US06242282B1

公开(公告)日：2001-06-05

申请号：US09411101

申请日：1999-10-04

申请人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

发明人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

IPC分类号： H01L2144

CPC分类号： H01L24/48 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/24227 ,  H01L2224/4824 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.

公开(公告)号：US06396153B2

公开(公告)日：2002-05-28

申请号：US09768598

申请日：2001-01-25

申请人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

发明人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

IPC分类号： H01L2348

CPC分类号： H01L24/48 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/24227 ,  H01L2224/4824 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.

摘要翻译： 一种用于封装至少一个电路芯片的方法包括：提供包括具有第一侧和第二侧的绝缘材料的互连层，在第二侧的第二侧金属化部分上而不是在第二侧非金属化部分上图案化的初始金属化 第二侧，至少一个从第一侧延伸到第二侧金属化部分之一的衬底通孔;以及至少一个芯片通孔，其从第一侧延伸到第二侧非金属化部分之一; 将所述至少一个电路芯片定位在所述第二侧上，所述至少一个电路芯片的至少一个芯片焊盘与所述至少一个芯片通孔对准; 以及在所述互连层的第一侧和所述通孔的选定部分上图案化连接金属化，以便延伸到所述至少一个第二侧金属化部分和所述至少一个芯片焊盘。 在相关实施例中，通孔被预先金属化并且通过导电粘合剂耦合到电路芯片的芯片焊盘。 薄膜无源元件和多层互连可另外包含在封装中。

公开(公告)号：US06507113B1

公开(公告)日：2003-01-14

申请号：US09443410

申请日：1999-11-19

申请人： Raymond Albert Fillion ,  Robert John Wojnarowski ,  Ronald Frank Kolc

发明人： Raymond Albert Fillion ,  Robert John Wojnarowski ,  Ronald Frank Kolc

IPC分类号： H01L2348

CPC分类号： H01L23/49838 ,  H01L23/49811 ,  H01L24/02 ,  H01L2224/02125 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12042 ,  H05K1/0271 ,  H05K1/114 ,  H05K3/326 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0367 ,  H05K2201/09663 ,  H01L2924/00012 ,  H01L2924/00

摘要： One type of electronic interface structure includes a base; at least one elastomeric island supported by the base; and patterned metallization overlying the at least one elastomeric island and including at least one floating pad at least partially overlying the at least one elastomeric island. Another type of electronic interface structure includes a base; a first dielectric layer overlying the base and having at least one first dielectric layer opening therein; a second dielectric layer overlying the first dielectric layer; and patterned metallization overlying the second dielectric layer and including at least one floating pad at least partially overlying the at least one opening.

摘要翻译： 电子接口结构的一种类型包括基座; 由基座支撑的至少一个弹性岛; 以及覆盖所述至少一个弹性体岛并且包括至少部分地覆盖所述至少一个弹性体岛的至少一个浮动垫的图案化金属化。 另一种类型的电子接口结构包括基座; 覆盖所述基底并且在其中开有至少一个第一介电层的第一介电层; 覆盖所述第一介电层的第二电介质层; 以及覆盖在所述第二介电层上并且包括至少部分地覆盖所述至少一个开口的至少一个浮动焊盘的图案化金属化。

公开(公告)号：US06410356B1

公开(公告)日：2002-06-25

申请号：US09520751

申请日：2000-03-07

申请人： Robert John Wojnarowski ,  Ernest Wayne Balch ,  Leonard Richard Douglas

发明人： Robert John Wojnarowski ,  Ernest Wayne Balch ,  Leonard Richard Douglas

IPC分类号： H01L2166

CPC分类号： H01L22/20 ,  H01L23/34 ,  H01L2224/92144 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/00

摘要： A method for interconnecting high-temperature silicon carbide (SiC) devices enables such high-temperature devices to be used in fabricating electronic circuits of significant scale. This method comprises empirically measuring operational characteristics of a plurality of the devices to be interconnected, the operational characteristics comprising devices which are measured to be non-working and devices which are measured to be working; characterizing the operational characteristics in an operational characteristics map; designing interconnection paths between and among the devices that are characterized to be working by the operational characteristics map; and excluding from the interconnection paths, devices that are characterized to be non-working by the operational characteristics map. A preferred embodiment of this method further includes disposing a temporary polymer layer over the devices; forming via holes through the temporary polymer layer, to bonding pads of the devices; applying a current-balancing resistive metal over the temporary polymer layer; establishing connections between the current-balancing resistive metal and the bonding pads; designing the interconnection paths between and among the working devices by patterning the current-balancing resistive metal based on the operational characteristics map; and removing the temporary polymer layer.

摘要翻译： 用于互连高温碳化硅（SiC）器件的方法使得这种高温器件能够用于制造具有显着规模的电子电路。 该方法包括经验地测量待互连的多个设备的操作特性，操作特性包括被测量为不工作的设备和被测量为工作的设备; 表征操作特征图中的操作特性; 设计特征在于通过操作特征图工作的设备之间的互连路径; 并且从互连路径中排除特征在于通过操作特性图不工作的设备。 该方法的优选实施例还包括在器件上设置临时聚合物层; 通过所述临时聚合物层形成通孔到所述装置的焊盘; 在临时聚合物层上施加电流平衡电阻金属; 建立电流平衡电阻金属和焊盘之间的连接; 通过基于操作特性图构图电流平衡电阻金属来设计工作装置之间和之间的互连路径; 并除去临时聚合物层。

公开(公告)号：US5872040A

公开(公告)日：1999-02-16

申请号：US862994

申请日：1997-05-27

申请人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

发明人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

IPC分类号： H01C17/12 ,  H01C17/24 ,  H01G4/06 ,  H01G4/08 ,  H05K1/16 ,  H01L21/20

CPC分类号： H01C17/24 ,  H01C17/12 ,  H01C17/2416 ,  H01G4/06 ,  H01G4/08 ,  H05K1/167 ,  Y10S148/136

摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.

摘要翻译： 提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。 电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。 薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。 可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。

公开(公告)号：US5683928A

公开(公告)日：1997-11-04

申请号：US349278

申请日：1994-12-05

申请人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

发明人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

IPC分类号： H01C17/12 ,  H01C17/24 ,  H01G4/06 ,  H01G4/08 ,  H05K1/16 ,  H01L21/70

CPC分类号： H01C17/24 ,  H01C17/12 ,  H01C17/2416 ,  H01G4/06 ,  H01G4/08 ,  H05K1/167 ,  Y10S148/136

摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.

摘要翻译： 提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。 电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。 薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。 可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。

公开(公告)号：US06603145B2

公开(公告)日：2003-08-05

申请号：US10136626

申请日：2002-05-02

申请人： Robert John Wojnarowski ,  Ernest Wayne Balch ,  Leonard Richard Douglas

发明人： Robert John Wojnarowski ,  Ernest Wayne Balch ,  Leonard Richard Douglas

IPC分类号： H01L310312

CPC分类号： H01L22/20 ,  H01L23/34 ,  H01L2224/92144 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/00

摘要： A method for interconnecting high-temperature silicon carbide (SiC) devices enables such high-temperature devices to be used in fabricating electronic circuits of significant scale. This method comprises empirically measuring operational characteristics of a plurality of the devices to be interconnected, the operational characteristics comprising devices which are measured to be non-working and devices which are measured to be working; characterizing the operational characteristics in an operational characteristics map; designing interconnection paths between and among the devices that are characterized to be working by the operational characteristics map; and excluding from the interconnection paths, devices that are characterized to be non-working by the operational characteristics map. A preferred embodiment of this method further includes disposing a temporary polymer layer over the devices; forming via holes through the temporary polymer layer, to bonding pads of the devices; applying a current-balancing resistive metal over the temporary polymer layer; establishing connections between the current-balancing resistive metal and the bonding pads; designing the interconnection paths between and among the working devices by patterning the current-balancing resistive metal based on the operational characteristics map; and removing the temporary polymer layer.

公开(公告)号：US6040226A

公开(公告)日：2000-03-21

申请号：US177908

申请日：1998-10-23

申请人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

发明人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

IPC分类号： H01L21/20

CPC分类号： H01L21/20

摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.

摘要翻译： 提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。 电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。 薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。 可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。

公开(公告)号：US06302987B1

公开(公告)日：2001-10-16

申请号：US09286329

申请日：1999-04-05

申请人： Robert John Wojnarowski ,  Clive William Reed ,  Thomas Bert Gorczyca

发明人： Robert John Wojnarowski ,  Clive William Reed ,  Thomas Bert Gorczyca

IPC分类号： B29C6552

CPC分类号： H02G5/005 ,  Y10T29/49945

摘要： A method for coupling electrically conductive bushings in a bus, including alternating layers of dielectric material and patterned, electrically conductive bus bars and having through holes therein with each through hole having a surface exposing a portion of a respective one of the bus bars, includes: applying a polymer mixture to the surface of each through hole; inserting the bushings in the respective through holes; and curing the polymer mixture by positioning the bus and bushings in a curing chamber, applying a vacuum to the curing chamber, and applying pressure to reduce voids in the polymer mixture and minimize further void formation.

摘要翻译： 一种用于在总线中耦合导电衬套的方法，包括介电材料和图案化的导电母线的交替层，并且在其中具有通孔，每个通孔具有露出相应一个母线的一部分的表面的方法包括： 将聚合物混合物施加到每个通孔的表面; 将衬套插入相应的通孔中; 并通过将母线和套管定位在固化室中，对固化室施加真空并施加压力以减小聚合物混合物中的空隙并使进一步的空隙形成最小化来固化聚合物混合物。

公开(公告)号：US5703400A

公开(公告)日：1997-12-30

申请号：US684715

申请日：1996-07-22

申请人： Robert John Wojnarowski ,  Thomas Bert Gorczyca

发明人： Robert John Wojnarowski ,  Thomas Bert Gorczyca

IPC分类号： H01L23/538 ,  H01L25/065 ,  H05K1/18 ,  H01L23/34 ,  H01L23/06

CPC分类号： H01L24/76 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/82 ,  H01L25/0652 ,  H05K1/185 ,  H05K1/186 ,  H01L2224/18 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K2201/10674 ,  H05K3/4611 ,  Y10S438/928

摘要： First and second flexible interconnect structures are provided and each includes a flexible interconnect layer and a chip with a surface having chip pads attached to the flexible interconnect layer. Molding material is inserted between the flexible interconnect layers for encapsulating the respective chips. Vias in the flexible interconnect layers are formed to extend to selected chip pads, and a pattern of electrical conductors is applied which extends over the flexible interconnect layers and into the vias to couple selected ones of the chip pads.

摘要翻译： 提供了第一和第二柔性互连结构，并且每个包括柔性互连层和具有连接到柔性互连层的具有芯片焊盘的表面的芯片。 将成型材料插入在柔性互连层之间以封装相应的芯片。 柔性互连层中的通孔形成为延伸到选定的芯片焊盘，并且施加电导体图案，该图案在柔性互连层上延伸并穿过通孔以耦合选定的芯片焊盘。