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1.发明授权Integrated resistor, phase-change memory element including this resistor, and process for the fabrication thereof 有权集成电阻器，包括该电阻器的相变存储元件及其制造方法公开(公告)号：US06946673B2
公开(公告)日：2005-09-20
申请号：US10345129
申请日：2003-01-14
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/008 , G11C2213/52 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion than in the second portion. Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi, TiSi2, Ta, WSi, and the increase in resistivity is obtained by nitridation.
摘要翻译： 垂直电流阻力元件包括具有第一部分和第二部分的整体区域，第一部分和第二部分彼此顶部布置并由单一材料形成。 第一部分具有第一电阻率，第二部分具有低于第一电阻率的第二电阻率。 为此目的，首先形成具有均匀的电阻率和高于其它尺寸中的至少一个的高度的整体区域; 那么通过从顶部引入与整体区域的导电材料形成普遍共价键的物质来增加第一部分的电阻率，使得所述物质的浓度在第一部分中比在第二部分中更高 。 优选地，导电材料是选自TiAl，TiSi，TiSi 2，Ta，WSi的二元或三元合金，并且通过氮化获得电阻率的增加。
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2.发明申请Process for manufacturing integrated resistor and phase-change memory element including this resistor 审中-公开集成电阻器和包括该电阻器的相变存储元件的制造工艺公开(公告)号：US20050269667A1
公开(公告)日：2005-12-08
申请号：US11201790
申请日：2005-08-11
申请人： Romina Zonca , Maria Marangon , Giorgio De Santi
发明人： Romina Zonca , Maria Marangon , Giorgio De Santi
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/008 , G11C2213/52 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion than in the second portion. Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi, TiSi2, Ta, WSi, and the increase in resistivity is obtained by nitridation.
摘要翻译： 垂直电流阻力元件包括具有第一部分和第二部分的整体区域，第一部分和第二部分彼此顶部布置并由单一材料形成。 第一部分具有第一电阻率，第二部分具有低于第一电阻率的第二电阻率。 为此目的，首先形成具有均匀的电阻率和高于其它尺寸中的至少一个的高度的整体区域; 那么通过从顶部引入与整体区域的导电材料形成普遍共价键的物质来增加第一部分的电阻率，使得所述物质的浓度在第一部分中比在第二部分中更高 。 优选地，导电材料是选自TiAl，TiSi，TiSi 2，Ta，WSi的二元或三元合金，并且通过氮化获得电阻率的增加。
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3.发明授权Fabricating a CMOS transistor having low threshold voltages using self-aligned silicide polysilicon gates and silicide interconnect regions 失效使用自对准硅化物多晶硅栅极和硅化物互连区域制造具有低阈值电压的CMOS晶体管
公开(公告)号：US4703552A
公开(公告)日：1987-11-03
申请号：US689875
申请日：1985-01-09
申请人： Livio Baldi , Giuseppe Corda , Giulio Iannuzzi , Danilo Re , Giorgio De Santi
发明人： Livio Baldi , Giuseppe Corda , Giulio Iannuzzi , Danilo Re , Giorgio De Santi
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/49 , H01L29/78 , H01L21/265 , H01L21/28
CPC分类号： H01L29/4933 , H01L21/823835 , Y10S148/082
摘要： The method provides for the formation of a layer of metal silicide on the gate layer of polycrystalline silicon and, for each transistor of the CMOS pair, the simultaneous doping of the active regions and the gate polycrystalline silicon. In the structure produced by this method, the gate electrodes are of polycrystalline silicon covered by metal silicide and the gate electrode of the n-channel transistor is doped with n-type material, while the gate electrode of the p-channel transistor is doped with p-type impurities. This enables the production of low threshold voltages for both transistors even in the case of very high integration densities.
摘要翻译： 该方法提供在多晶硅的栅极层上形成金属硅化物层，并且对于CMOS对的每个晶体管，同时掺杂有源区和栅极多晶硅。 在通过该方法制造的结构中，栅电极是由金属硅化物覆盖的多晶硅，并且n沟道晶体管的栅电极掺杂有n型材料，而p沟道晶体管的栅电极掺杂 p型杂质。 这使得即使在非常高的集成密度的情况下也可以为两个晶体管产生低阈值电压。
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4.发明授权Process and structure for measuring the planarity degree of a dielectric layer in an integrated circuit and integrated circuit including means for performing said process 失效用于测量集成电路中的电介质层的平面度的集成电路和集成电路的工艺和结构，包括用于执行所述工艺的装置
公开(公告)号：US5543633A
公开(公告)日：1996-08-06
申请号：US92717
申请日：1993-07-15
摘要： A method for measuring the degree of planarity in an integrated circuit includes depositing, onto a dielectric layer to be measured for planarity, a predetermined measure path of a conductive film and measuring the electric resistance of said measure path. The resistance of such a measure path is minimal where the surface on which it has been deposited is perfectly planar, and increases with the surface deviation from perfect planarity. An integrated circuit containing a measurement portion of conductive film and a reference portion of conductive film is described.
摘要翻译： 一种用于测量集成电路中的平面度的方法包括：将待测量的电介质层平坦化地沉积在导电膜的预定测量路径上并测量所述测量路径的电阻。 这种测量路径的电阻在其沉积的表面是完全平坦的时是最小的，并且随着与完美平面性的表面偏差而增加。 描述了包含导电膜的测量部分和导电膜的参考部分的集成电路。
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5.发明授权Process for forming semiconductor device having multi-thickness metallization 失效用于形成具有多厚度金属化的半导体器件的工艺
公开(公告)号：US4718977A
公开(公告)日：1988-01-12
申请号：US773319
申请日：1985-09-06
IPC分类号： H01L23/52 , H01L21/28 , H01L21/3205 , H01L23/532 , C23F1/02 , H01L29/44
CPC分类号： H01L23/53223 , H01L2924/0002
摘要： Structure and method for metallization patterns of different thicknesses on a semiconductor device or integrated circuit. The improved structure and method utilizes three layers of metal in order to reduce the required number of processing steps. One preferred embodiment entails a single metal deposition sequence followed by two etch steps, while a second embodiment, suitable for thicker metallization, requires only two depositions and two etch steps.
摘要翻译： 半导体器件或集成电路上不同厚度的金属化图案的结构和方法。 改进的结构和方法利用三层金属，以减少所需数量的加工步骤。 一个优选实施例需要单个金属沉积序列，随后是两个蚀刻步骤，而适用于较厚金属化的第二实施例仅需要两个沉积和两个蚀刻步骤。
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公开(公告)号：US06888225B2
公开(公告)日：2005-05-03
申请号：US10323961
申请日：2002-12-18
申请人： Giorgio De Santi , Luca Zanotti
发明人： Giorgio De Santi , Luca Zanotti
IPC分类号： H01L21/314 , H01L21/316 , H01L21/318 , H01L23/31 , H01L23/58
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/3145 , H01L21/31612 , H01L21/3185 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： A process for forming a final passivation layer over an integrated circuit comprises a step of forming, over a surface of the integrated circuit, a protective film by means of High-Density Plasma Chemical Vapor Deposition.
摘要翻译： 用于在集成电路上形成最终钝化层的方法包括在集成电路的表面上通过高密度等离子体化学气相沉积形成保护膜的步骤。
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公开(公告)号：US06187683B1
公开(公告)日：2001-02-13
申请号：US09059740
申请日：1998-04-14
IPC分类号： H01L21311
CPC分类号： H01L21/31053 , H01L21/31051 , H01L21/31055 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： A planarization method is disclosed to provide improved protection against cracking of the final passivation layer of integrated circuit devices. In one embodiment, such method includes final passivation of an integrated circuit device including at least one integrated circuit chip. Such final passivation includes the step of forming a layer of protective material over a top surface of the integrated circuit chip, and a subsequent step of planarizing such layer of protective material to obtain a protection layer having a substantially flat top surface.
摘要翻译： 公开了一种平面化方法，以提供改进的防止集成电路器件的最终钝化层破裂的保护。 在一个实施例中，这种方法包括包括至少一个集成电路芯片的集成电路器件的最终钝化。 这种最终钝化包括在集成电路芯片的顶表面上形成保护材料层的步骤，以及随后的平坦化这种保护材料层以获得具有基本平坦的顶表面的保护层的步骤。
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8.发明授权Low dielectric constant composite film for integrated circuits of an inorganic aerogel and an organic filler grafted to the inorganic material 失效用于无机气凝胶和接枝到无机材料上的有机填料的集成电路的低介电常数复合膜和制造方法
公开(公告)号：US6087729A
公开(公告)日：2000-07-11
申请号：US62378
申请日：1998-04-17
IPC分类号： C01B33/12 , C08F292/00 , C08L51/10 , H01B3/30 , H01L21/312 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/485
CPC分类号： H01B3/30 , C08F292/00 , H01L23/5329 , H01L2924/0002 , Y02P20/544
摘要： An insulating film between stacked electrically conducting layers through which interconnections of integrated circuits are realized, is formed of an aerogel of an inorganic oxide on which organic monomers have been grafted under inert ion bombardment and successively further incorporated in the aerogel to fill at least partially the porosities of the inorganic aerogel. The composite dielectric material is thermally stable and has a satisfactory thermal budget. The method of forming an aerogel film includes the spinning of a precursor compound solution onto the wafer followed by supercritical solvent extraction carried out in the spinning chamber.
摘要翻译： 层叠的导电层之间的绝缘膜通过其形成集成电路的互连，其中无机氧化物的气凝胶由有机单体在惰性离子轰击下接枝并依次进一步掺入气凝胶中以至少部分地填充 无机气凝胶的孔隙率。 复合介电材料是热稳定的并且具有令人满意的热预算。 形成气凝胶膜的方法包括将前体化合物溶液旋转到晶片上，然后在纺丝室中进行超临界溶剂萃取。
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