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    Pixel sensor cells and methods of manufacturing
    1.
    发明授权
    Pixel sensor cells and methods of manufacturing 有权
    像素传感器单元和制造方法

    公开(公告)号：US08592244B2

    公开(公告)日：2013-11-26

    申请号：US13189961

    申请日：2011-07-25

    申请人： Jeffrey P. Gambino ,  Robert K. Leidy ,  Mark D. Levy

    发明人： Jeffrey P. Gambino ,  Robert K. Leidy ,  Mark D. Levy

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14623 ,  H01L27/14636 ,  H01L27/14687

    摘要： Pixel sensor cells with an opaque mask layer and methods of manufacturing are provided. The method includes forming a transparent layer over at least one active pixel and at least one dark pixel of a pixel sensor cell. The method further includes forming an opaque region in the transparent layer over the at least one dark pixel.

    摘要翻译： 提供了具有不透明掩模层的像素传感器单元和制造方法。 该方法包括在像素传感器单元的至少一个有源像素和至少一个暗像素的上方形成透明层。 该方法还包括在至少一个暗像素上的透明层中形成不透明区域。

    Discontinuous guard ring
    3.
    发明授权
    Discontinuous guard ring 有权
    不连续的护环

    公开(公告)号：US08729664B2

    公开(公告)日：2014-05-20

    申请号：US13437273

    申请日：2012-04-02

    申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

    发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

    IPC分类号： H01L29/15 ,  H01L23/52 ,  H01L29/47 ,  H01L27/095

    CPC分类号： H01L29/0619 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.

    摘要翻译： 一种集成电路芯片，包括形成在半导体衬底上的保护环，所述保护环围绕所述集成电路芯片的有源区并从所述半导体衬底延伸穿过多个布线层中的一个或多个。 保护环包括堆叠金属线，空间分开各个金属线。 每个空间可以被形成为使得其部分地覆盖金属线中的空间直接在下方，但不覆盖任何其它空间。 或者，每个空间也可以形成为使得每个空间至少完全覆盖在其下面的金属线中的空间。

    DISCONTINUOUS GUARD RING
    4.
    发明申请
    DISCONTINUOUS GUARD RING 有权
    不连续的保护环

    公开(公告)号：US20130256826A1

    公开(公告)日：2013-10-03

    申请号：US13437273

    申请日：2012-04-02

    申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

    发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

    IPC分类号： H01L29/06

    CPC分类号： H01L29/0619 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.

    摘要翻译： 一种集成电路芯片，包括形成在半导体衬底上的保护环，所述保护环围绕所述集成电路芯片的有源区并且从所述半导体衬底延伸通过多个布线层中的一个或多个。 保护环包括堆叠金属线，空间分开各个金属线。 每个空间可以被形成为使得其部分地覆盖金属线中的空间直接在下方，但不覆盖任何其它空间。 或者，每个空间也可以形成为使得每个空间至少完全覆盖在其下面的金属线中的空间。

    Multi-run selective pattern and etch wafer process
    6.
    发明授权
    Multi-run selective pattern and etch wafer process 失效
    多运行选择性图案和蚀刻晶圆工艺

    公开(公告)号：US07060626B2

    公开(公告)日：2006-06-13

    申请号：US10604087

    申请日：2003-06-25

    申请人： Kenneth A. Bandy ,  Vincent J. Carlos ,  Mark D. Levy ,  Sara L. Lucas ,  Timothy C. Milmore ,  Matthew C. Nicholls ,  Jason Nowakowski

    发明人： Kenneth A. Bandy ,  Vincent J. Carlos ,  Mark D. Levy ,  Sara L. Lucas ,  Timothy C. Milmore ,  Matthew C. Nicholls ,  Jason Nowakowski

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/31144

    摘要： A method for forming a semiconductor wafer comprising of applying a first patterned resist to at least one first predetermined region of a wafer where said at least one first predetermined region of said wafer are protected by said first patterned resist and a first remaining portion of said wafer is not protected by said first patterned resist; etching said first remaining portion of said wafer not protected by said first pattern resist; stripping the first pattern resist from said wafer; applying a second patterned resist to at least one second pre-determined region of said wafer where said at least one second predetermined region of said wafer are protected by a second patterned resist and a second remaining portion is not protected by said second patterned resist; etching said second remaining portion not protected by said second patterned resist; and stripping said second patterned resist from said wafer.

    摘要翻译： 一种用于形成半导体晶片的方法，包括将第一图案化抗蚀剂施加到晶片的至少一个第一预定区域，其中所述晶片的所述至少一个第一预定区域被所述第一图案化抗蚀剂保护并且所述晶片的第一剩余部分 不受所述第一图案化抗蚀剂的保护; 蚀刻所述晶片的未被所述第一图案抗蚀剂保护的所述第一剩余部分; 从所述晶片剥离第一图案抗蚀剂; 将第二图案化抗蚀剂施加到所述晶片的至少一个第二预定区域，其中所述晶片的所述至少一个第二预定区域被第二图案化抗蚀剂保护，并且第二剩余部分不被所述第二图案化抗蚀剂保护; 蚀刻不被所述第二图案化抗蚀剂保护的所述第二剩余部分; 以及从所述晶片剥离所述第二图案化抗蚀剂。