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公开(公告)号：US20140095908A1
公开(公告)日：2014-04-03
申请号：US14095982
申请日：2013-12-03
IPC分类号： G06F1/32
CPC分类号： H04W52/0225 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3296 , G06F13/4282 , H04L43/0858 , Y02D10/151 , Y02D70/00 , Y02D70/142 , Y02D70/23
摘要： For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，可以识别对于下游设备的至少一部分从第一状态到第二不同状态的转变。 第一和第二状态可以对应于与下游设备的至少一部分的活动有关的不同级别。 响应于所识别的一个或多个上游设备的转换，至少部分地基于服务等待时间来对应于服务等待时间的数据可被发送到上游设备以管理电力。 还公开了其他实施例。
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公开(公告)号：US20160252942A1
公开(公告)日：2016-09-01
申请号：US14633438
申请日：2015-02-27
申请人： Ankush Varma , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , Krishnakanth V. Sistla , James G. Hermerding, II
发明人： Ankush Varma , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , Krishnakanth V. Sistla , James G. Hermerding, II
CPC分类号： G06F1/263 , G06F1/206 , G06F1/3212 , G06F1/324 , G06F15/00 , Y02D10/126 , Y02D10/16 , Y02D10/174
摘要： In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，系统包括：多个计算节点，用于耦合在机架中; 第一共享电源，用于向所述多个计算节点提供基线功率电平; 以及辅助电源，用于在比基线功率电平更高的功率电平的操作期间向多个计算节点中的一个或多个提供电力。 描述和要求保护其他实施例。
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公开(公告)号：US06438622B1
公开(公告)日：2002-08-20
申请号：US09193269
申请日：1998-11-17
申请人： Siamack Haghighi , Neil W. Songer
发明人： Siamack Haghighi , Neil W. Songer
IPC分类号： G06F1300
CPC分类号： G06F1/1632 , G06F15/7864
摘要： A system includes a docking base unit having a first processor and a portable computing device that is dockable to the docking base unit that includes a second processor. A module identifies the number of processors in the system once the portable computing device is docked to the docking base unit and configures the system as a multiprocessor system if more than one processor is identified.
摘要翻译： 系统包括具有第一处理器和便携式计算设备的对接基座单元，该便携式计算设备可对接到包括第二处理器的对接基座单元。 一旦便携式计算设备对接到对接基座单元，则模块识别系统中的处理器数量，并且如果识别出多于一个的处理器，则将系统配置为多处理器系统。
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公开(公告)号：US20140101470A1
公开(公告)日：2014-04-10
申请号：US14101545
申请日：2013-12-10
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3215 , G06F1/3228
摘要： For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，可以接收对应于一个或多个下游设备的空闲持续时间的数据。 可以至少部分地基于所接收的数据来管理功率。 还公开了其他实施例。
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公开(公告)号：US20120254644A1
公开(公告)日：2012-10-04
申请号：US13077727
申请日：2011-03-31
申请人： William Knolla , Douglas R. Moran , Neil W. Songer
发明人： William Knolla , Douglas R. Moran , Neil W. Songer
IPC分类号： G06F1/32
CPC分类号： G06F1/3209
摘要： Embodiments of methods and apparatus for entering an activity alignment on state from an activity alignment off state; masking one or more traffic flows that are received during at least a part of the activity alignment on state; and entering the activity alignment off state from the activity alignment on state, after being in the activity alignment on state for at least a first time period, based at least in part on said masking the one or more traffic flows. Additional variants and embodiments are also disclosed.
摘要翻译： 用于从活动对准关闭状态进入状态的活动对准的方法和装置的实施例; 掩蔽在活动对齐状态的至少一部分期间接收的一个或多个业务流; 以及至少部分地基于所述屏蔽所述一个或多个业务流，在所述活动对齐状态之后，在所述活动对齐状态之后，在处于所述活动对准状态至少第一时间段之后进入所述活动对齐关闭状态。 还公开了其它变型和实施方案。
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6.发明授权Method and apparatus for providing a processor module for a computer system 失效用于为计算机系统提供处理器模块的方法和装置
公开(公告)号：US6041372A
公开(公告)日：2000-03-21
申请号：US774515
申请日：1996-12-30
申请人： Frank P. Hart , Ravi Nagaraj , James L. Noble , Neil W. Songer
发明人： Frank P. Hart , Ravi Nagaraj , James L. Noble , Neil W. Songer
CPC分类号： G06F13/4068
摘要： A method and apparatus for converting a signal from a first voltage level to a second voltage level before providing the signal to a processor. A circuit board includes an interface for coupling the circuit board to a peripheral subsystem via a socket. The circuit board also includes a processor that receives signals of a first voltage level, a first signal line, and a second signal line. The first signal line is coupled to the interface and provides a reference signal to the peripheral subsystem that indicates the first voltage level. The second signal line is also coupled to the interface and provides a subsystem signal back from the peripheral subsystem after the signal has been converted to the first voltage level.
摘要翻译： 一种用于在将信号提供给处理器之前将信号从第一电压电平转换为第二电压电平的方法和装置。 电路板包括用于经由插座将电路板耦合到外围子系统的接口。 电路板还包括接收第一电压电平，第一信号线和第二信号线的信号的处理器。 第一信号线耦合到接口，并向指示第一电压电平的外围子系统提供参考信号。 第二信号线还耦合到接口并且在信号已被转换到第一电压电平之后从外围子系统提供子系统信号。
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7.发明授权Method and apparatus for handling bus master channel and direct memory access (DMA) channel access requests at an I/O controller 失效用于在I / O控制器处理总线主通道和直接存储器访问（DMA）通道访问请求的方法和装置
公开(公告)号：US5664197A
公开(公告)日：1997-09-02
申请号：US426825
申请日：1995-04-21
申请人： James P. Kardach , Sung-Soo Cho , Jim S. Cheng , Debra T. Cohen , John W. Horigan , Nader Raygani , Seyed Yahay Sotoudeh , David I. Poisner , Neil W. Songer
发明人： James P. Kardach , Sung-Soo Cho , Jim S. Cheng , Debra T. Cohen , John W. Horigan , Nader Raygani , Seyed Yahay Sotoudeh , David I. Poisner , Neil W. Songer
IPC分类号： G06F13/28 , G06F13/30 , G06F13/364 , G06F13/00
CPC分类号： G06F13/28 , G06F13/30 , G06F13/364
摘要： A computer system that implements a direct memory access (DMA) request passing protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. The PCI bus is coupled to at least one DMA agent and a DMA controller. The DMA agent issues DMA requests to the DMA controller using the electrical interface of the PCI bus. According to one embodiment, a system I/O controller receives the DMA requests and passes them on to the DMA controller, which arbitrates the DMA requests and passes back a grant to the system I/O controller. The system I/O controller uses the electrical interface of the PCI bus to pass the grant to the DMA agent. The same DMA request passing protocol may be implemented in any bus having an electrical interface that specifies a unique request signal line for each bus agent of the bus.
摘要翻译： 实现直接存储器访问（DMA）请求传递协议的计算机系统。 计算机系统可以包括外围组件互连（PCI）总线，其包括由PCI本地总线标准指定的电接口。 PCI总线耦合到至少一个DMA代理和DMA控制器。 DMA代理使用PCI总线的电接口向DMA控制器发出DMA请求。 根据一个实施例，系统I / O控制器接收DMA请求并将它们传递到DMA控制器，DMA控制器对DMA请求进行仲裁，并将授权传回给系统I / O控制器。 系统I / O控制器使用PCI总线的电接口将授权传递给DMA代理。 相同的DMA请求传递协议可以在具有为总线的每个总线代理指定唯一请求信号线的电接口的任何总线中实现。
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公开(公告)号：US20160239068A1
公开(公告)日：2016-08-18
申请号：US14623764
申请日：2015-02-17
申请人： ANKUSH VARMA , KRISHNAKANTH V. SISTLA , VASUDEVAN SRINIVASAN , EUGENE GORBATOV , ANDREW D. HENROID , BARNES COOPER , DAVID W. BROWNING , GUY M. THERIEN , NEIL W. SONGER , JAMES G. HERMERDING, II
发明人： ANKUSH VARMA , KRISHNAKANTH V. SISTLA , VASUDEVAN SRINIVASAN , EUGENE GORBATOV , ANDREW D. HENROID , BARNES COOPER , DAVID W. BROWNING , GUY M. THERIEN , NEIL W. SONGER , JAMES G. HERMERDING, II
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/3203 , G06F1/3287 , G06F9/50 , Y02B70/126 , Y02D10/171
摘要： In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括执行指令的至少一个核心和用于从多个设备接收功率能力信息的功率控制逻辑以耦合到处理器并且向设备分配平台功率预算，为 分配相应设备被供电的设备将第一功率电平传送到设备，并且动态地减少要分配给第一设备的第一功率并且增加要分配给第二设备的第二功率，以响应于 来自第二设备的更高功率电平的请求。 描述和要求保护其他实施例。
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公开(公告)号：US20150006923A1
公开(公告)日：2015-01-01
申请号：US13927746
申请日：2013-06-26
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/3234 , G06F1/3243 , Y02D10/152
摘要： In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括多个核心和电源管理逻辑。 功率管理逻辑可以是响应于处理器中的降低功率状态期间的第一中断事件而设置基于平台等待时间容限的退出定时器，阻止第一多个中断事件中断降低的功率状态，以及 响应于退出定时器的到期，终止降低的功率状态。 描述和要求保护其他实施例。
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公开(公告)号：US08607075B2
公开(公告)日：2013-12-10
申请号：US12347573
申请日：2008-12-31
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3215 , G06F1/3228
摘要： For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，可以接收对应于一个或多个下游设备的空闲持续时间的数据。 可以至少部分地基于所接收的数据来管理功率。 还公开了其他实施例。
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