公开(公告)号：US06642554B2

公开(公告)日：2003-11-04

申请号：US09996675

申请日：2001-11-21

申请人： Nai Hua Yeh ,  Chen Pin Peng ,  Chief Lin ,  C. S. Cheng ,  Kuang Yu Fan ,  Ren Long Kau ,  Fu Yung Huang ,  Yves Huang ,  Wu Hsiang Lee ,  Chih Hsien Chung ,  May Chen

发明人： Nai Hua Yeh ,  Chen Pin Peng ,  Chief Lin ,  C. S. Cheng ,  Kuang Yu Fan ,  Ren Long Kau ,  Fu Yung Huang ,  Yves Huang ,  Wu Hsiang Lee ,  Chih Hsien Chung ,  May Chen

IPC分类号： H01L31072

CPC分类号： G11C5/04 ,  H05K1/181 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/10689 ,  Y02P70/611

摘要： A memory module structure of the invention is used for being assembled on a locking device. The memory module includes a substrate and a plurality of memories. The substrate has certain long sides and short sides. Notches are formed on the short sides for being secured by the locking device. Each of the plurality of memories has a suitable length and width. Some memories of the plurality of memories are transversely mounted on the substrate with respect to the substrate. The other memories of the plurality of memories are longitudinally mounted on the substrate with respect to the substrate. According to this structure, it is possible to suitably arrange a plurality of memories on the substrate so as to increase the memory capacity of the memory module.

摘要翻译： 本发明的存储器模块结构用于组装在锁定装置上。 存储器模块包括衬底和多个存储器。 基板有一定的长边和短边。 在短边上形成凹口以由锁定装置固定。 多个存储器中的每一个具有合适的长度和宽度。 多个存储器的一些存储器相对于衬底横向地安装在衬底上。 多个存储器的其它存储器相对于衬底纵向地安装在衬底上。 根据该结构，可以在基板上适当地配置多个存储器，以增加存储器模块的存储容量。

公开(公告)号：US06565008B2

公开(公告)日：2003-05-20

申请号：US10018072

申请日：2001-12-04

申请人： Mon Nan Ho ,  Hsiu Wen Tu ,  Kuo Feng Feng ,  Yung Sheng Chiu ,  Joe Liu ,  Nai Hua Yeh ,  Wen Chuan Chen ,  Allis Chen

发明人： Mon Nan Ho ,  Hsiu Wen Tu ,  Kuo Feng Feng ,  Yung Sheng Chiu ,  Joe Liu ,  Nai Hua Yeh ,  Wen Chuan Chen ,  Allis Chen

IPC分类号： G06K1906

CPC分类号： H01L23/49855 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A manufacturing method of a module card comprises steps of: providing a base board having a golden finger; mounting a chip on the base board for electrically connecting to the golden finger; and forming a packing layer on the chip for forming the module card. A module card comprises: a base board; a chip mounting on a surface of the base board; a golden finger on the board and electrically connecting to the chip; and a packing layer forming on the chip for covering the chip.

摘要翻译： 模块卡的制造方法包括以下步骤：提供具有金手指的基板; 在基板上安装芯片以电连接到金手指; 以及在芯片上形成用于形成模块卡的填充层。 模块卡包括：基板; 芯片安装在基板的表面上; 一个金手指在电路板上并与芯片电连接; 以及形成在芯片上用于覆盖芯片的填充层。

公开(公告)号：US06559539B2

公开(公告)日：2003-05-06

申请号：US09770084

申请日：2001-01-24

申请人： Hsiu Wen Tu ,  Wen Chuan Chen ,  Mon Nan Ho ,  Li Huan Chen ,  Nai Hua Yeh ,  Yen Cheng Huang ,  Yung Sheng Chiu ,  Jichen Wu

发明人： Hsiu Wen Tu ,  Wen Chuan Chen ,  Mon Nan Ho ,  Li Huan Chen ,  Nai Hua Yeh ,  Yen Cheng Huang ,  Yung Sheng Chiu ,  Jichen Wu

IPC分类号： H01L2334

CPC分类号： H01L25/0657 ,  H01L31/0203 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/16195 ,  H01L2924/1627 ,  H01L2924/00 ,  H01L2224/0401

摘要： A stacked package structure of an image sensor used for electrically connecting to a printed circuit board includes a substrate, an image sensing chip, an integrated circuit, and a transparent layer. The substrate has a first surface and a second surface. The first surface is formed with signal input terminals. The second surface is formed with signal input terminals and signal output terminals for electrically connecting to the printed circuit board. The image sensing chip is mounted on the first surface of the substrate and is electrically to the signal input terminals of the substrate. The integrated circuit is arranged on the second surface of the substrate and is electrically connected to the signal input terminals of the substrate. The transparent layer covers over the image sensing chip, which can receive the image signals via the transparent layer and convert the image signals into electrical signals that are to be transmitted to the substrate. Thus, the image sensing chip of the image sensing product and integrated circuit can be integrally packaged.

摘要翻译： 用于电连接到印刷电路板的图像传感器的堆叠封装结构包括基板，图像感测芯片，集成电路和透明层。 基板具有第一表面和第二表面。 第一表面由信号输入端子形成。 第二表面形成有用于电连接到印刷电路板的信号输入端子和信号输出端子。 图像感测芯片安装在基板的第一表面上并且电连接到基板的信号输入端子。 集成电路布置在基板的第二表面上并且电连接到基板的信号输入端子。 透明层覆盖图像感测芯片，其可以经由透明层接收图像信号，并将图像信号转换成要传输到基板的电信号。 因此，图像感测产品和集成电路的图像感测芯片可以被整体封装。

公开(公告)号：US06501187B1

公开(公告)日：2002-12-31

申请号：US09996691

申请日：2001-11-21

申请人： Nai Hua Yeh ,  Chen Pin Peng ,  Chief Lin ,  Ching-Shui Cheng ,  Allis Chen

发明人： Nai Hua Yeh ,  Chen Pin Peng ,  Chief Lin ,  Ching-Shui Cheng ,  Allis Chen

IPC分类号： H01L2328

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2224/85 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package structure having central leads according to the invention includes a substrate, a semiconductor device, a plurality of wires, and glue. A long slot penetrating through the substrate is formed in the substrate. A plurality of bonding pads formed on the semiconductor device are mounted on substrate. The plurality of bonding pads on the semiconductor device are exposed via the long slot of the substrate. The length of the semiconductor device is smaller than that of the long slot of the substrate so that a channel is formed at one side of the long slot when the semiconductor device is mounted on the substrate. The plurality of wires are arranged within the long slot of the substrate for electrically connecting the plurality of bonding pads on the semiconductor device to the plurality of signal output terminals on the substrate. The glue is provided for sealing the upper surface of the substrate to protect the semiconductor device. The glue is poured into the long slot of the substrate via the channel formed by the long slot of the substrate, for covering the plurality of wires.

摘要翻译： 根据本发明的具有中心引线的半导体封装结构包括衬底，半导体器件，多根电线和胶水。 在衬底中形成穿过衬底的长槽。 形成在半导体器件上的多个接合焊盘安装在基板上。 半导体器件上的多个接合焊盘经由衬底的长槽露出。 半导体器件的长度小于衬底的长槽的长度，使得当半导体器件安装在衬底上时，在长槽的一侧形成沟道。 多个布线布置在基板的长槽内，用于将半导体器件上的多个接合焊盘电连接到基板上的多个信号输出端子。 提供胶水以密封衬底的上表面以保护半导体器件。 通过由衬底的长槽形成的通道将胶水注入衬底的长槽中，以覆盖多根电线。

公开(公告)号：US06472736B1

公开(公告)日：2002-10-29

申请号：US10097822

申请日：2002-03-13

申请人： Nai Hua Yeh ,  Chen Pin Peng

发明人： Nai Hua Yeh ,  Chen Pin Peng

IPC分类号： H01L2302

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/5385 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked structure for memory chips includes a substrate, a lower memory chip, an upper memory chip, and an insulation medium. The substrate has an upper surface, a lower surface and a slot penetrating through the substrate from the upper surface to the lower surface. The lower memory chip has a central portion formed with a plurality of bonding pads. The lower memory chip is arranged on the upper surface of the substrate. The plurality of bonding pads is exposed via the slot of the substrate, and the bonding pads are electrically connected to the lower surface of the substrate via a plurality of wires. The upper memory chip has a central portion formed with a plurality of bonding pads. The upper memory chip is arranged on the lower memory chip in a back-to-back manner with respect to the lower memory chip so that the plurality of bonding pads of the upper memory chip faces upwards. The insulation medium has a central portion formed with a slot. The plurality of bonding pads of the upper memory chip is exposed via the slot of the insulation medium. The insulation medium is formed with a plurality of traces electrically connecting to the bonding pads of the upper memory chip and the upper surface of the substrate via a plurality of wires. Accordingly, the length and radian of each wire can be reduced so that a better signal transmission effect and a smaller package volume can be obtained.

摘要翻译： 用于存储芯片的叠层结构包括基板，下存储芯片，上存储芯片和绝缘介质。 基板具有从上表面到下表面穿过基板的上表面，下表面和狭槽。 下部存储器芯片具有形成有多个接合焊盘的中心部分。 下部存储器芯片布置在基板的上表面上。 多个接合焊盘经由衬底的槽暴露，并且焊盘通过多根电线电连接到衬底的下表面。 上存储芯片具有形成有多个接合焊盘的中心部分。 上部存储器芯片相对于下部存储器芯片以背靠背的方式布置在下部存储器芯片上，使得上部存储器芯片的多个焊盘面朝上。 绝缘介质具有形成有槽的中心部分。 上存储芯片的多个接合焊盘通过绝缘介质的槽露出。 绝缘介质形成有多条迹线，其经由多根电线电连接到上存储芯片的接合焊盘和衬底的上表面。 因此，可以减少每条线的长度和弧度，从而可以获得更好的信号传输效果和更小的封装体积。

公开(公告)号：US06400007B1

公开(公告)日：2002-06-04

申请号：US09836107

申请日：2001-04-16

申请人： Jichen Wu ,  Meng Ru Tsai ,  Nai Hua Yeh ,  Chen Pin Peng

发明人： Jichen Wu ,  Meng Ru Tsai ,  Nai Hua Yeh ,  Chen Pin Peng

IPC分类号： H01L2302

CPC分类号： H01L24/32 ,  H01L23/3128 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： An stacked structure of semiconductor means and method for manufacturing the same, comprises a substrate, a lower semiconductor chip, an adhered glue layer, a plurality of wires and an upper semiconductor chip. The adhered glue layer located between the substrate and the lower semiconductor to adhere the lower semiconductor to the substrate. The overflow glue of the adhered glue layer covered above the periphery of the lower semiconductor chip. The plurality of wires each being electrically connected to the lower semiconductor chip and the substrate, so that each wires are located above the overflow glue. The upper semiconductor chip is located above lower semiconductor chip and electrically connected to the substrate.

摘要翻译： 半导体装置的叠层结构及其制造方法包括基板，下半导体芯片，粘合胶层，多根导线和上半导体芯片。 位于基板和下半导体之间的粘附胶层将下半导体粘附到基板上。 粘合胶层的溢出胶被覆盖在下半导体芯片周围的上方。 多个电线各自电连接到下半导体芯片和基板，使得每个电线位于溢流胶上方。 上半导体芯片位于下半导体芯片的上方并与基板电连接。

公开(公告)号：US06642137B2

公开(公告)日：2003-11-04

申请号：US10147029

申请日：2002-05-15

申请人： Nai Hua Yeh ,  Chen Pin Peng ,  Jichen Wu

发明人： Nai Hua Yeh ,  Chen Pin Peng ,  Jichen Wu

IPC分类号： H01L2144

CPC分类号： H01L24/83 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L29/0657 ,  H01L2224/05599 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/07802 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/10155 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package structure for an integrated circuit includes a substrate, an integrated circuit, an adhesive layer, a plurality of wirings, and a glue layer. The substrate has a first surface and a second surface. The first surface is formed with a plurality of signal input terminals. The second surface is formed with a plurality of signal output terminals for electrically connecting to the circuit board. The integrated circuit has a lower surface and an upper surface. Recesses are formed at two sides of the lower surface, and a plurality of bonding pads are formed on the upper surface. The adhesive layer is used for adhering the lower surface of the integrated circuit to the first surface of the substrate. The wirings are electrically connecting to the bonding pads of the integrated circuit and to the signal input terminals of the substrate. The glue layer is used for sealing the plurality of wirings and the integrated circuits. According to the structure, the problem caused by the overflowed glue in the integrated circuit can be effectively avoided. A method for manufacturing the structure is also disclosed.

公开(公告)号：US06627983B2

公开(公告)日：2003-09-30

申请号：US09770083

申请日：2001-01-24

申请人： Hsiu Wen Tu ,  Wen Chuan Chen ,  Mon Nan Ho ,  Li Huan Chen ,  Nai Hua Yeh ,  Yen Cheng Huang ,  Yung Sheng Chiu ,  Jichen Wu ,  Joe Liu ,  Wu Hsiang Lee

发明人： Hsiu Wen Tu ,  Wen Chuan Chen ,  Mon Nan Ho ,  Li Huan Chen ,  Nai Hua Yeh ,  Yen Cheng Huang ,  Yung Sheng Chiu ,  Jichen Wu ,  Joe Liu ,  Wu Hsiang Lee

IPC分类号： H01L2302

CPC分类号： H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/00014

摘要： A stacked package structure of an image sensor for electrically connecting to a printed circuit board includes a first substrate, a second substrate, an integrated circuit, an image sensing chip, and a transparent layer. The second substrate is mounted on the first substrate so as to a cavity formed between the first substrate and second substrate. The integrated circuit is located within the cavity and electrically connected the first substrate. The image-sensing chip is arranged on the second substrate. The transparent layer covers over the image sensing chip, wherein the image sensing chip receives image signals via the transparent layer and transforms the image signals into electrical signals transmitted to the first substrate. Thus, the image sensing chip of the image sensing product and the integrated circuit can be integrally package.