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公开(公告)号：US09128662B2
公开(公告)日：2015-09-08
申请号：US13720951
申请日：2012-12-19
发明人： Jin-Ki Kim , Dae-Hee Yi
CPC分类号： G06F1/16 , G06F1/1658 , G06F3/0626 , G06F3/0658 , G06F3/0688 , G11C7/1003
摘要： A solid-state drive architecture and arrangement for standardized disk drive form factors, PCI type memory cards and general motherboard memory. The solid-state drive architecture is modular in that a main printed circuit board (PCB) of the memory system includes a host interface connector, a memory controller, and connectors. Each connector can removably receive a memory blade, where each memory blade includes a plurality of memory devices serially connected to each other via a serial interface. Each memory blade includes a physical serial interface for providing data and control signals to a first memory device in the serial chain and for receiving data and control signals from a last memory device in the serial chain. Each memory blade can be sized in length and width to accommodate any number of memory devices on either side thereof.
摘要翻译： 一种用于标准化磁盘驱动器外形尺寸的固态驱动架构和布局，PCI型存储卡和通用主板内存。 固态驱动架构是模块化的，其中存储器系统的主印刷电路板（PCB）包括主机接口连接器，存储器控制器和连接器。 每个连接器可移除地接收存储器刀片，其中每个存储器刀片包括通过串行接口彼此串行连接的多个存储器件。 每个存储器刀片包括物理串行接口，用于向串行链中的第一存储器件提供数据和控制信号，并用于从串行链中的最后一个存储器件接收数据和控制信号。 每个存储器刀片的尺寸可以在长度和宽度上以适应其任一侧上的任何数量的存储器件。
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公开(公告)号：US09159374B2
公开(公告)日：2015-10-13
申请号：US13665181
申请日：2012-10-31
发明人： Jin-Ki Kim , DaeHee Yi , HyoShin Kim
CPC分类号： G11C5/04 , G11C7/1003
摘要： A mass storage memory module system including a memory module having memory holding members which can be connected to each other, and removably connected to a memory controller. One or more modular memory holding members can be connected to each other to expand the overall storage capacity of the memory module. The presently described expandable memory module does not have a storage capacity limit. A memory holding member includes a plate, a plane, a board and another material having at least one memory device, or, on which at least one memory device is held or to which at least one memory device is mounted.
摘要翻译： 一种大容量存储器模块系统，包括具有能够彼此连接的存储器保持部件的存储器模块，并且可移除地连接到存储器控制器。 一个或多个模块化存储器保持构件可以彼此连接以扩展存储器模块的总体存储容量。 目前描述的可扩展存储器模块不具有存储容量限制。 存储器保持构件包括板，平面，板和具有至少一个存储器件的另一种材料，或者在其上保持至少一个存储器件或至少一个存储器件被安装在该存储器件上。
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公开(公告)号：US09054717B2
公开(公告)日：2015-06-09
申请号：US14066748
申请日：2013-10-30
发明人： Hong Beom Pyeon
摘要： A method, system and apparatus to provide a solution of PLL locking issue in the daisy chained memory system. A first embodiment uses consecutive PLL on based on locking status of backward device on the daisy chained memory system with no requirement of PLL locking status checking pin. A second embodiment uses Flow through PLL control with a locking status pin either using an existing pin or a separated pin. A third embodiment uses a relocking control mechanism to detect PLL relocking from the device. A fourth variation uses flag signal generation to send to the controller.
摘要翻译： 一种在菊花链式存储器系统中提供PLL锁定问题的方法，系统和装置。 第一实施例基于菊花链存储器系统上的后向装置的锁定状态而使用连续的PLL，而不需要PLL锁定状态检查引脚。 第二个实施例使用通过PLL控制的流量通过锁定状态引脚来使用现有的引脚或分离的引脚。 第三实施例使用重新锁定控制机制来检测来自装置的PLL重新锁定。 第四变体使用标志信号发生来发送到控制器。
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公开(公告)号：US09476938B2
公开(公告)日：2016-10-25
申请号：US14478824
申请日：2014-09-05
发明人： Hong Beom Pyeon , Young-Goan Kim
IPC分类号： G11C29/00 , G01R31/317 , G01R31/3181 , G11C29/12 , G11C29/56 , G11C16/00 , G11C29/26
CPC分类号： G01R31/31713 , G01R31/31701 , G01R31/31813 , G11C16/00 , G11C29/1201 , G11C29/56 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus comprising a plurality of devices connected in series with one another, each of the devices comprising a test enable pin for receiving a test enable signal that indicates enablement of a test mode, and a test output pin for outputting a test output signal in the test mode, and a controller coupled to the devices and comprising an additional test output pin for outputting a test channel output signal, wherein a failure of at least one of the test output signals and the test channel output signal indicates the existence of one or more potential defects associated with the plurality of devices and the controller.
摘要翻译： 一种装置，包括彼此串联连接的多个装置，每个装置包括用于接收指示启用测试模式的测试使能信号的测试使能引脚和用于输出测试输出信号的测试输出引脚 测试模式和耦合到所述设备的控制器，并且包括用于输出测试通道输出信号的附加测试输出引脚，其中所述测试输出信号和测试通道输出信号中的至少一个的故障指示存在一个或多个 与多个设备和控制器相关联的潜在缺陷。
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公开(公告)号：US09471484B2
公开(公告)日：2016-10-18
申请号：US13835968
申请日：2013-03-15
发明人： HakJune Oh , Jin-Ki Kim , Young Goan Kim , Hyun Woong Lee
CPC分类号： G06F12/0246 , G06F13/1668 , G06F13/1694 , G06F13/385
摘要： A memory controller of a data storage device, which communicates with a host, is configurable to have at least two different pinout assignments for interfacing with respective different types of memory devices. Each pinout assignment corresponds to a specific memory interface protocol. Each memory interface port of the memory controller includes port buffer circuitry configurable for different functional signal assignments, based on the selected memory interface protocol to be used. The interface circuitry configuration for each memory interface port is selectable by setting a predetermined port or registers of the memory controller.
摘要翻译： 与主机进行通信的数据存储设备的存储器控制器可配置为具有用于与相应不同类型的存储器件接口的至少两个不同的引脚分配。 每个引脚分配对应于特定的存储器接口协议。 存储器控制器的每个存储器接口端口基于所使用的选择的存储器接口协议，包括可配置用于不同功能信号分配的端口缓冲器电路。 通过设置存储器控制器的预定端口或寄存器来选择每个存储器接口端口的接口电路配置。
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6.发明授权公开(公告)号：US09159647B2
公开(公告)日：2015-10-13
申请号：US13750046
申请日：2013-01-25
发明人： Byoung Jin Choi
CPC分类号： H01L23/48 , G11C5/04 , G11C5/063 , H01L21/50 , H01L25/0652 , H01L2224/16225 , H01L2225/06517 , H01L2225/06527 , H01L2225/06548 , H01L2225/06572 , H05K1/0243 , H05K1/181 , H05K2201/10159 , H05K2201/10545
摘要： A method, system and apparatus for connecting multiple memory device dies 51-54 to a substrate 56 which requires no trace between dies. A first embodiment assigns the connections of a memory device die 51 to be matched with other memory device dies 52-54 when mounted in staggered formation on the both sides of a substrate. The result is a daisy chained array connecting multiple integrated circuits with reduced capacitive loading. The capacitive loadings on the buses 57,58 between memory device dies 51,52,53 are reduced. The number of vias 57,58,59 is reduced because two stubs on the both sides of the substrate share one via. Another embodiment FIG. 7 arranges the dies in a closed loop.
摘要翻译： 一种用于将多个存储器件管芯51-54连接到不需要管芯之间的痕迹的衬底56的方法，系统和装置。 第一实施例将存储器件管芯51的连接分配成与其它存储器件管芯52-54匹配，当安装在衬底两侧的交错形成时。 结果是连接多个具有降低的电容负载的集成电路的菊花链阵列。 存储器件管芯51,52,53之间的总线57,58上的电容负载减小。 通孔57,58,59的数量减少，因为衬底的两侧上的两个短截线共享一个通孔。 另一实施例图 7将模具排列在闭环中。
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7.发明授权Clock reproducing and timing method in a system having a plurality of devices 有权具有多个装置的系统中的时钟再现和定时方法公开(公告)号：US09148277B2
公开(公告)日：2015-09-29
申请号：US14294372
申请日：2014-06-03
发明人： Hong Beom Pyeon , Peter Gillingham
CPC分类号： H04L7/0331 , G06F13/1689 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/06562 , Y02D10/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data. The memory controller provides a clock signal for synchronizing the operations of the devices. Each device includes a phase-locked loop (PLL) that is selectively enabled or disabled by a PLL enable signal. In each group, the PLLs of a selected number of devices are enabled by PLL enable signals and the other devices are disabled. The enabled PLL provides a plurality of reproduced clock signals with a phase shift of a multiple of 90° in response to an input clock signal. The data transfer is synchronized with at least one of the reproduced clock signals. In the devices of disabled PLLs, the data transfer is synchronized with the input clock signal. The enabled PLL and disabled PLL cause the devices to be the source and the common synchronous clocking, respectively. The devices can be grouped. The devices of one group can be structured by multiple chip packages.
摘要翻译： 系统包括存储器控制器和串联连接的多个半导体器件。 每个设备具有用于存储数据的存储器核心。 存储器控制器提供用于同步器件的操作的时钟信号。 每个器件包括被PLL使能信号选择性地使能或禁止的锁相环（PLL）。 在每个组中，选定数量的器件的PLL通过PLL使能信号使能，其他器件被禁止。 所启用的PLL响应于输入时钟信号提供多个具有90°的倍数的相移的再现时钟信号。 数据传输与再现的时钟信号中的至少一个同步。 在禁用PLL的器件中，数据传输与输入时钟信号同步。 使能的PLL和禁用的PLL分别使器件成为源和公共同步时钟。 设备可以分组。 一组的器件可以由多个芯片封装构成。
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