公开(公告)号：US08520391B2

公开(公告)日：2013-08-27

申请号：US13112253

申请日：2011-05-20

Applicant: Huei-Nuan Huang ,  Pin-Cheng Huang ,  Chun-Hung Lu ,  Chun-Chieh Chao ,  Chi-Hsin Chiu

Inventor： Huei-Nuan Huang ,  Pin-Cheng Huang ,  Chun-Hung Lu ,  Chun-Chieh Chao ,  Chi-Hsin Chiu

IPC: H05K7/20

CPC classification number: H01L25/0657 ,  B82Y30/00 ,  H01L21/486 ,  H01L23/142 ,  H01L23/367 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  Y10T29/49139 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2224/05552

Abstract: An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity.

Abstract translation: 公开了一种内层散热板和具有内层散热板的多芯片堆叠封装结构。 内层散热板包括形成有多个穿透导电通孔的金属板体，每个穿透导电通孔包括多个纳米线，以及具有填充有纳米线的纳米孔的氧化块。 多芯片堆叠封装结构包括分别设置在内层散热板上的第一芯片和电子部件，从而促进多芯片堆叠结构中的散热以及增加整体封装刚性。

公开(公告)号：US20130020709A1

公开(公告)日：2013-01-24

申请号：US13242940

申请日：2011-09-23

Applicant: Chun-An Huang ,  Pin-Cheng Huang ,  Chi-Hsin Chiu ,  Shih-Kuang Chiu

Inventor： Chun-An Huang ,  Pin-Cheng Huang ,  Chi-Hsin Chiu ,  Shih-Kuang Chiu

IPC: H01L23/488 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/1148 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/13339 ,  H01L2224/13347 ,  H01L2224/16237 ,  H01L2224/29011 ,  H01L2224/29076 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/73204 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00014

Abstract: A semiconductor package and a method of fabricating the same. The semiconductor package includes a carrier having a plurality bonding pads disposed on a surface thereof, a packaging layer formed on the surface of the carrier and having a plurality of openings corresponding to the bonding pads, a conductive material filled in the openings and electrically connected to the bonding pads, and an electronic component installed on the packaging layer and having a plurality of conductive pillars correspondingly received in the openings and electrically connected to the conductive material. The formation of the openings in the packaging layer can control the position and size of the conductive material to enable the overall height of the conductive structure to be level and to keep the electronic component from tilting.

Abstract translation: 一种半导体封装及其制造方法。 半导体封装包括具有设置在其表面上的多个焊盘的载体，形成在载体的表面上并具有对应于接合焊盘的多个开口的封装层，填充在开口中的导电材料并电连接到 接合焊盘和安装在包装层上的电子部件，并且具有相应地容纳在开口中并电连接到导电材料的多个导电柱。 包装层中的开口的形成可以控制导电材料的位置和尺寸，以使得导电结构的整体高度水平并且保持电子部件不会倾斜。

公开(公告)号：US20140073087A1

公开(公告)日：2014-03-13

申请号：US13680728

申请日：2012-11-19

Applicant: Pin-Cheng Huang ,  Yi-Che Lai

Inventor： Pin-Cheng Huang ,  Yi-Che Lai

IPC: H01L21/56

CPC classification number: H01L21/56 ,  H01L21/486 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: A method of fabricating a semiconductor package is provided, including: providing a substrate having opposite first and second surfaces and a plurality of conductive through holes penetrating the first and second surfaces, disposing the substrate on a first carrier through the second surface thereof, and keeping the first carrier flat and free of warpage; attaching at least a first semiconductor chip to the first surface of the substrate and electrically connecting the first semiconductor chip and the substrate; removing the first carrier; and attaching the substrate to a packaging substrate through the second surface thereof and electrically connecting the substrate and the packaging substrate, thereby preventing the semiconductor package from warpage, increasing product yield, reducing fabrication cost, and improving thermal dissipation.

Abstract translation: 提供了一种制造半导体封装的方法，包括：提供具有相反的第一和第二表面的基板和穿过第一和第二表面的多个导电通孔，通过其第二表面将基板设置在第一载体上，并保持 第一个承运人平坦，无翘曲; 将至少第一半导体芯片附接到所述基板的所述第一表面并电连接所述第一半导体芯片和所述基板; 移除第一载体; 并通过其第二表面将衬底附着到封装衬底上，并电连接衬底和封装衬底，从而防止半导体封装翘曲，提高产品产量，降低制造成本，并改善热耗散。

公开(公告)号：US20120224328A1

公开(公告)日：2012-09-06

申请号：US13112253

申请日：2011-05-20

Applicant: Huei-Nuan Huang ,  Pin-Cheng Huang ,  Chun-Hung Lu ,  Chun-Chieh Chao ,  Chi-Hsin Chiu

Inventor： Huei-Nuan Huang ,  Pin-Cheng Huang ,  Chun-Hung Lu ,  Chun-Chieh Chao ,  Chi-Hsin Chiu

IPC: H05K7/20 ,  H05K3/32 ,  H05K1/02 ,  B82Y99/00

CPC classification number: H01L25/0657 ,  B82Y30/00 ,  H01L21/486 ,  H01L23/142 ,  H01L23/367 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  Y10T29/49139 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2224/05552

Abstract: An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity.

Abstract translation: 公开了一种内层散热板和具有内层散热板的多芯片堆叠封装结构。 内层散热板包括形成有多个穿透导电通孔的金属板体，每个穿透导电通孔包括多个纳米线，以及具有填充有纳米线的纳米孔的氧化块。 多芯片堆叠封装结构包括分别设置在内层散热板上的第一芯片和电子部件，从而促进多芯片堆叠结构中的散热以及增加整体封装刚性。

公开(公告)号：US20120168936A1

公开(公告)日：2012-07-05

申请号：US13243646

申请日：2011-09-23

Applicant: Pin-Cheng Huang ,  Chun-Chieh Chao ,  Chi-Hsin Chiu

Inventor： Pin-Cheng Huang ,  Chun-Chieh Chao ,  Chi-Hsin Chiu

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/17181 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: A multi-chip stack package structure includes: an inner-layer heat sink having a first surface and a second surface opposing one another and having a plurality of conductive vias penetrating the first surface and the second surface; a first chip disposed on the first surface of the inner-layer heat sink; and a second chip disposed on the second surface of the inner-layer heat sink. Thereby, a heat-dissipating path is provided within inner-layers of the multi-chip stack package structure, and the rigidity of the overall structure is enhanced.

Abstract translation: 多芯片堆叠封装结构包括：具有第一表面和第二表面的内层散热器，所述第一表面和第二表面彼此相对并具有穿过所述第一表面和所述第二表面的多个导电通孔; 设置在所述内层散热器的第一表面上的第一芯片; 以及设置在所述内层散热器的第二表面上的第二芯片。 由此，在多芯片堆叠封装结构的内层设置有散热路径，提高了整体结构的刚性。