公开(公告)号：US20250169074A1

公开(公告)日：2025-05-22

申请号：US18515968

申请日：2023-11-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gang LIU ,  Santosh MENON

IPC: H10B43/30 ,  H01L21/28 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/66 ,  H10B69/00

Abstract: One illustrative integrated circuit manufacturing method includes: a sequence of process operations to provide bipolar devices, CMOS (complementary metal oxide semiconductor) devices, and DMOS (double-diffused metal oxide semiconductor) devices on a monolithic integrated circuit substrate; and further operations to provide nonvolatile memory cells on the monolithic integrated circuit substrate with no additional thermal budget, with no additional implant operations, and with only a single additional mask, relative to the sequence of process operations. The sequence of process operations includes one or more ion implantation operations to form wells and/or buried layers for the bipolar devices, the CMOS devices, and the DMOS devices, on a shared integrated circuit substrate; an annealing operation to heal damage from the one or more ion implantation operations before forming sources and drains for the CMOS and DMOS devices; and gate formation operations to form gates for the CMOS devices and the DMOS devices.

公开(公告)号：US20250167672A1

公开(公告)日：2025-05-22

申请号：US19029746

申请日：2025-01-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Anders Soren LIND

IPC: H02M1/42 ,  H02M1/00 ,  H02M1/08 ,  H02M3/157 ,  H02M7/5388

Abstract: An apparatus for controlling a power converter operable to receive a cyclically varying input signal includes a discrete-time, on-time generator coupled to the power converter and operable to regulate an output voltage of the power converter and a controller operable to compare the output voltage of the power converter against a voltage range or threshold to: obtain a comparison result in synchronization with the cyclically varying input signal and select one of a plurality of operation levels of the discrete-time, on-time generator in response to the comparison result. The plurality of operation levels may include a linear, discrete-time operation level and a nonlinear, discrete-time operation level. The nonlinear, discrete-time operation level may include determining a power deficiency of a bulk capacitor and adjusting a width of an on-time pulse accordingly.

公开(公告)号：US12298127B2

公开(公告)日：2025-05-13

申请号：US17666740

申请日：2022-02-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jacques Jean Bertin

IPC: G01B7/00 ,  G01D5/20

Abstract: A position of a target is determined using a linear inductive position sensor that includes a target coil, an excitation coil, two sensors and a Vernier processor. The sensors each include two or more receive coils. The receive coils include multiple twisted loops. In the first sensor, the coils have a first period, with loops offset by first distance. In the second sensor, the coils have a second period, with loops offset by a second distance. The target coil width is a function of the first distance and the second distance. During operation, the coils output voltages in which third, fifth and/or seventh harmonics are cancelled. Based on the voltages, the sensors output respective first and second position signals, from which the Vernier processor calculates the target's position along an axis of the position sensor.

公开(公告)号：US20250140659A1

公开(公告)日：2025-05-01

申请号：US18941178

申请日：2024-11-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Maria Cristina ESTACIO ,  Seungwon IM

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/473 ,  H10D62/832

Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.

公开(公告)号：US12284834B2

公开(公告)日：2025-04-22

申请号：US18777737

申请日：2024-07-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Derrick Johnson ,  Yupeng Chen ,  Ralph N. Wall ,  Mark Griswold

IPC: H10D89/60 ,  H10D84/85

Abstract: In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.

公开(公告)号：US20250125284A1

公开(公告)日：2025-04-17

申请号：US18488628

申请日：2023-10-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  David T. PRICE ,  Marc Allen SULFRIDGE ,  Richard MAURITZSON ,  James Joseph STEFFES

IPC: H01L23/60 ,  H01L23/00 ,  H01L27/146

Abstract: A semiconductor device may include a first chip with a first wafer and a first dielectric layer, and a second chip that includes a second wafer and a second dielectric layer, the second chip having a backside surface and a frontside surface opposed to the backside surface and bonded to the first chip at the frontside surface to define a bond line between the first dielectric layer and the second dielectric layer. The semiconductor device may include a die seal layer on the backside surface having a die seal ground contact in contact with the second wafer, and an electrostatic discharge path that includes the die seal layer, the die seal ground contact, a first die seal in the first dielectric layer, a second die seal in the second dielectric layer, and a hybrid bond connecting the first die seal and the second die seal through the bond line.

公开(公告)号：US20250118640A1

公开(公告)日：2025-04-10

申请号：US18987230

申请日：2024-12-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Yusheng LIN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/24 ,  H01L23/31 ,  H01L23/538 ,  H01L25/18

Abstract: Implementations of a semiconductor package may include a first substrate including a first group of leads physically coupled thereto and a second group of leads physically coupled thereto; a second substrate coupled over the first substrate and physically coupled to the first group of leads and the second group of leads; and one or more semiconductor die coupled between the first substrate and the second substrate. The second group of leads may be electrically isolated from the first substrate.

公开(公告)号：US12272747B2

公开(公告)日：2025-04-08

申请号：US17643539

申请日：2021-12-09

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Joseph Andrew Yedinak

IPC: H01L29/78 ,  H01L21/225 ,  H01L29/167 ,  H01L29/40 ,  H01L29/66

Abstract: In an aspect, an electronic device can include a substrate, a semiconductor layer overlying the substrate and including a mesa adjacent to a trench, and a doped region within the semiconductor layer. The doped region extends across an entire width of the mesa and contacts the lowermost point of the trench. A charge pocket can be located between an elevation of the peak concentration of the doped region and an elevation of the upper surface of the substrate. In another aspect, a process includes patterning a semiconductor layer to define a trench, forming a sacrificial layer within the trench, removing the sacrificial layer from a bottom of the trench, doping a portion of the semiconductor layer that is along the bottom of the trench while a remaining portion of the sacrificial layer is along a sidewall of the trench.

公开(公告)号：US20250102651A1

公开(公告)日：2025-03-27

申请号：US18631649

申请日：2024-04-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Marek HUSTAVA

IPC: G01S7/521 ,  G01S15/10 ,  G01S15/87 ,  G01S15/931

Abstract: Illustrative sensor controllers, sensors, sensing systems, and sensing methods, may enable cost-efficient implementation of ADAS (advanced driver-assistance system) features with hidden sensors. As one example, an illustrative sensing method includes: transmitting an acoustic burst through a surface over an ultrasonic transducer; receiving an acoustic signal with a MEMS (micro-electromechanical systems) microphone, the MEMS microphone representing the acoustic signal as an electrical receive signal; and processing the electrical receive signal to detect a reflection of the acoustic burst.

公开(公告)号：US20250096679A1

公开(公告)日：2025-03-20

申请号：US18468400

申请日：2023-09-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jaume ROIG-GUITART ,  Dean E. PROBST

IPC: H02M3/158 ,  H03K17/687

Abstract: In a general aspect, a circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) having a gate, a source, and a drain. The MOSFET has a first breakdown voltage. The circuit also includes a clamping circuit coupled between the drain and the source. The clamping circuit including a diode having a second breakdown voltage that is less than the first breakdown voltage. A cathode of the diode is coupled with the drain of the MOSFET. The clamping circuit further includes an inductor having a first terminal coupled with an anode of the diode, and a second terminal coupled with the source of the MOSFET.