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公开(公告)号：US6093930A
公开(公告)日：2000-07-25
申请号：US54013
申请日：1998-04-02
申请人： James Edward Boyette, Jr. , James Michael Hammond , Salvatore R. Riggio, Jr. , Michael Servedio
发明人： James Edward Boyette, Jr. , James Michael Hammond , Salvatore R. Riggio, Jr. , Michael Servedio
IPC分类号： G01Q70/02 , G01Q70/14 , H01J37/067
CPC分类号： G01Q70/02 , B82Y35/00 , Y10S977/86
摘要： A scanning probe microscope having a probe attachment fixture, to which a probe assembly is removably attached during measurements, driven in an engagement direction, and a sample stage driven in scanning directions perpendicular to the engagement direction includes a buffer with a number of buffer stations within the sample stage. When the stage is driven so that one of the buffer stations is in alignment with the attachment fixture, and when the attachment fixture is driven in the engagement direction to be in proximity to the buffer station, the probe assembly is selectively transferred in either direction between the attachment fixture and the buffer station. In a preferred embodiment, probe assemblies are transferred on transfer pallets, and a stationary magazine is provided for storing these pallets, which are transferred in either direction between the magazine and the buffer.
摘要翻译： 一种扫描探针显微镜，其具有探针附接固定装置，探测器组件在测量期间以接合方向被驱动而可移除地附接到该探针附件，并且沿垂直于接合方向的扫描方向驱动的样本台包括具有多个缓冲站的缓冲器， 样品阶段。 当舞台被驱动使得缓冲站中的一个与附接夹具对准时，并且当附接夹具沿接合方向被驱动以接近缓冲站时，探针组件选择性地在 附件夹具和缓冲站。 在优选实施例中，探针组件被转移到转移托盘上，并且提供固定盒以存储这些托盘，这些托盘在盒和缓冲器之间沿任一方向传送。
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2.发明授权Non-volatile serial-to-parallel converter system utilizing thin-film, floating-gate, amorphous transistors 失效利用薄膜，浮栅，非晶晶体管的非易失性串并转换器系统
公开(公告)号：US5557272A
公开(公告)日：1996-09-17
申请号：US261352
申请日：1994-06-16
IPC分类号： G11C17/00 , G11C16/04 , G11C19/00 , G11C19/28 , G11C19/38 , H01L21/8247 , H01L27/115 , H01L27/12 , H01L29/788 , H01L29/792 , H03M9/00
CPC分类号： H01L27/115 , G11C19/38 , H01L27/1203
摘要： A serial-to-parallel converter comprises a plurality of amorphous silicon thin-film transistors configured in a plurality of serial-to-parallel converter cells through which data is shifted through a plurality of amorphous silicon thin-film floating-gate transistors. In the event power is cutoff or lost, the floating gate transistors non-volatilely store the data which can be read when power is subsequently turned on. Each cell comprises two stages in which data signals are written before being input into the next stage and next cell. A clock generator receives clocking signals for controlling the shifting of data through the serial-to-parallel converter.
摘要翻译： 串并转换器包括配置在多个串并转换器单元中的多个非晶硅薄膜晶体管，数据通过多个非晶硅薄膜晶体管偏移穿过多个非晶硅薄膜浮栅晶体管。 在电源切断或丢失的情况下，浮动栅极晶体管非易失地存储随后接通电源时可读取的数据。 每个单元包括在输入到下一个单元和下一个单元之前写入数据信号的两个阶段。 时钟发生器接收时钟信号，用于控制数据通过串行到并行转换器的移位。
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3.发明授权Non-volatile parallel-to-serial converter system utilizing thin-film floating-gate, amorphous transistors 失效利用薄膜浮栅非晶体晶体管的非易失性并行 - 串行转换器系统
公开(公告)号：US5543791A
公开(公告)日：1996-08-06
申请号：US260658
申请日：1994-06-16
IPC分类号： H01L21/8247 , G11C19/38 , H01L25/04 , H01L25/18 , H01L27/115 , H01L27/12 , H01L29/786 , H01L29/788 , H01L29/792 , H03M9/00
CPC分类号： G11C19/38 , H01L27/115 , H01L27/1203
摘要： A parallel-to-serial converter comprises a plurality of amorphous silicon thin-film transistors configured in a plurality of parallel-to-serial converter cells through which data is shifted through a plurality of amorphous silicon thin-film floating-gate transistors. In the event power is cutoff or lost, the floating gate transistors non-volatilely store the data which can be read when power is subsequently turned on. Each cell comprises two stages in which data signals are written before being input into the next stage and next cell. A clock generator receives clocking signals for controlling the shifting of data through the parallel-to-serial converter.
摘要翻译： 并行串行转换器包括多个并联到串行转换器单元的非晶硅薄膜晶体管，多个非晶硅薄膜晶体管通过多个非晶硅薄膜浮栅晶体管偏移数据。 在电源切断或丢失的情况下，浮动栅极晶体管非易失地存储随后接通电源时可读取的数据。 每个单元包括在输入到下一个单元和下一个单元之前写入数据信号的两个阶段。 时钟发生器接收时钟信号，用于控制通过并行到串行转换器的数据移位。
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公开(公告)号：US5528137A
公开(公告)日：1996-06-18
申请号：US377547
申请日：1995-01-24
CPC分类号： G01R31/2841 , G01R27/02 , G01R27/28
摘要： A network sensitive pulse generator circuit and a method of using the circuit to quickly detect faults in a net under test are described. The novel circuit generates pulses which depend upon the transient behavior of the net under test. The stimulation of the net and the sensing of the net's response operate responsively to a feedback signal, which is also a signature signal. By connecting the net under test to the novel circuit, the combination of the novel circuit and the net under test generates a series of output pulses. The number of pulses generated in a predetermined period of time forms the signature of the net under test. A preferred embodiment is described which uses differential amplifiers to stimulate the net and to sense the net's response. The differential amplifier which senses the net's response is connected to a circuit which produces the feedback/signature signal. The feedback/signal is then provide to the differential amplifiers to adjust their behavior.
摘要翻译： 描述了网络敏感脉冲发生器电路和使用该电路来快速检测被测网络中的故障的方法。 新颖的电路产生的脉冲依赖于被测网络的瞬态特性。 对网络的刺激和网络响应的感测响应于反馈信号，其也是签名信号。 通过将被测网络连接到新电路，新电路和被测网络的组合产生一系列输出脉冲。 在预定时间段内产生的脉冲数形成被测网络的签名。 描述了使用差分放大器来刺激网并感测网的响应的优选实施例。 感测网络响应的差分放大器连接到产生反馈/签名信号的电路。 然后将反馈/信号提供给差分放大器以调整其行为。
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公开(公告)号：US5502673A
公开(公告)日：1996-03-26
申请号：US503959
申请日：1995-07-19
IPC分类号： G11C17/00 , G11C16/04 , G11C19/28 , H01L21/8247 , H01L29/788 , H01L29/792 , H03K3/356 , G11C16/06
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of amorphous silicon thin-film transistors configured in a plurality of register cells through which data is shifted through a plurality of amorphous silicon thin-film floating-gate transistors. In the event power is cutoff or lost, the floating gate transistors non-volatilely store the data which can be recovered or restored when power is subsequently turned on. Each cell comprises two stages in which data signals are written before being input into the next stage and next cell. A clock generator receives clocking signals for controlling the shifting of data through the register.
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6.发明授权Battery powered magnetic pen having oscillator with improved efficiency and low power consumption 失效电池供电的磁笔具有提高效率和低功耗的振荡器
公开(公告)号：US5345197A
公开(公告)日：1994-09-06
申请号：US003083
申请日：1993-01-11
CPC分类号： G06F3/03545 , H03B5/1203 , H03B5/1231 , H03B5/1296
摘要： A battery-powered, magnetic-pen oscillator includes a circuit having a first transistor arranged in a common emitter configuration. A feedback loop includes a transformer and the transistor that produce a loop phase shift of zero degrees and a loop gain of one to cause oscillation, and additionally creates the magnetic field emitted by the pen. A second transistor provides current mirror biasing for the first transistor and determines the amount of current flowing through the first transistor.
摘要翻译： 电池供电的磁笔振荡器包括具有以共同发射器配置布置的第一晶体管的电路。 反馈回路包括变压器和产生零度的环路相移的晶体管和一个产生振荡的环路增益，并且另外产生由笔发射的磁场。 第二晶体管为第一晶体管提供电流镜偏置，并确定流经第一晶体管的电流量。
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公开(公告)号：US5142165A
公开(公告)日：1992-08-25
申请号：US575774
申请日：1990-08-31
CPC分类号： G06F1/28 , G06F1/24 , G06F1/30 , H02J9/061 , Y10S323/901 , Y10T307/858
摘要： The present off/on delay circuit operates within the power supply of a microcomputer system to interrupt transfer of regulated DC voltage to the system microcomputer and attachments in respect to indications of power disturbance and system switch status produced in the supply. Upon termination of such indications, this circuit selectively delays reappearance of regulated DC voltage to the level required for system operation so that whenever the microcomputer resets, the attachments must also reset; thereby preventing lockout impasses in the system rebooting process. The circuit operates in response to a plurality of DC voltage indications in the power supply, including at least an indication distinguishing the state of AC source power as either good or bad, and an indication distinguishing the state of a manually operable system power switch as either on or off. In one embodiment, the delay in reappearance of regulated DC operating voltage is chosen to be either relatively fast or slow depending upon how long the system operating voltage has been deactivated. Thus, the slow delay is chosen so as to effectively lengthen the effects of short duration outages or disturbances sufficiently to preclude lockout.
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公开(公告)号：US5539306A
公开(公告)日：1996-07-23
申请号：US451966
申请日：1995-05-26
CPC分类号： G01R31/2841 , G01R27/02 , G01R27/28
摘要： An apparatus is disclosed for quickly testing individual wiring nets in a multi-layer device carrier. A central processing unit (CPU) controls a probe to sequentially engage contact pads on the carrier, each of which is electrically connected to a respective wiring net. The probe connects each wiring net to a network sensitive pulse generator circuit which generates a train of output pulses having a frequency dependent upon the transient behavior of the net under test. The stimulation of the net and the sensing of the net's response operate responsively to a feedback signal, which is also a signature signal. By connecting the net under test to the novel circuit, the combination of the novel circuit and the net under test generates the series of output pulses. The number of pulses generated in a predetermined period of time forms the signature of the net under test. A preferred embodiment is described which uses differential amplifiers to stimulate the net and to sense the net's response. The differential amplifier which senses the net's response is connected to a circuit which produces the feedback/signature signal. The feedback/signal is then provided to the differential amplifiers to adjust their behavior. A novel pulse counting and interface circuit counts each series of output pulses received from the network sensitive pulse generator in a predetermined period of time; and, under control of the CPU, transfers each count to the CPU for evaluation by programs contained therein.
摘要翻译： 公开了一种用于在多层设备载体中快速测试各个接线网的装置。 中央处理单元（CPU）控制探头以顺序地接合载体上的接触垫，每个接触垫电连接到相应的接线网。 探头将每个接线网络连接到网络敏感脉冲发生器电路，该电路产生一系列具有取决于被测试网络的瞬态特性的频率的输出脉冲串。 对网络的刺激和网络响应的感测响应于反馈信号，其也是签名信号。 通过将被测网络连接到新电路，新电路和被测网络的组合产生一系列输出脉冲。 在预定时间段内产生的脉冲数形成被测网络的签名。 描述了使用差分放大器来刺激网并感测网的响应的优选实施例。 感测网络响应的差分放大器连接到产生反馈/签名信号的电路。 然后将反馈/信号提供给差分放大器以调整它们的行为。 一种新颖的脉冲计数和接口电路在预定时间段内对从网络敏感脉冲发生器接收的每个输出脉冲串进行计数; 并且在CPU的控制下，通过其中包含的程序将每个计数传送到CPU进行评估。
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9.发明授权
公开(公告)号：US5463339A
公开(公告)日：1995-10-31
申请号：US261351
申请日：1994-06-16
IPC分类号： H03K3/3565 , H03K3/295
CPC分类号： H03K3/3565
摘要： A driver circuit has hysteresis. The driver circuit includes a comparator circuit having first and second inputs and an output. The driver circuit also includes a variable voltage divider circuit coupled between the second input and the output of said comparator. The voltage divider circuit provides a first voltage to the second input of the comparator when the output of the comparator is at a second voltage, and a third voltage to the second input of the comparator when the output of the comparator is at a fourth voltage. Therefore, the output voltage of the comparator switches from the second to the fourth voltage when the voltage of a signal at the first input of the comparator rises above the first voltage, and the output voltage of the comparator switches from the fourth to the second voltage when the voltage of the signal at the first input of the comparator falls below the third voltage.
摘要翻译： 驱动电路具有迟滞。 驱动器电路包括具有第一和第二输入和输出的比较器电路。 驱动器电路还包括耦合在第二输入端和所述比较器的输出端之间的可变分压器电路。 当比较器的输出处于第二电压时，分压器电路向比较器的第二输入端提供第一电压，当比较器的输出为第四电压时，比较器的输出为第二电压，而比较器的第二输入端提供第三电压。 因此，当比较器的第一输入端的信号的电压上升到高于第一电压时，比较器的输出电压从第二电压切换到第四电压，并且比较器的输出电压从第四电压切换到第二电压 当比较器的第一输入处的信号的电压低于第三电压时。
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10.发明授权Apparatus and method for testing circuits by the response of a phase-locked loop 失效通过锁相环的响应测试电路的装置和方法
公开(公告)号：US5596280A
公开(公告)日：1997-01-21
申请号：US491020
申请日：1995-06-15
摘要： A PLL (phase-locked loop) circuit is used in apparatus for testing individual circuits in circuit devices. The PLL circuit operates at an input frequency provided by the output of an input oscillator when this oscillator is connected to one of the inputs of a phase comparator within the PLL circuit. When this connection is not made, the PLL circuit operates at a freerunning frequency, which is varied by connecting a circuit under test with a frequency controlling node present within a voltage-controlled oscillator in the PLL circuit. In a first mode of operation, the circuit under test is initially connected to the frequency controlling node, but the input oscillator is not connected to the phase comparator. When the input oscillator is so connected, the frequency of oscillations moves from a freerunning frequency associated with the circuit under test to the input frequency. During this transient behavior, the output of a loop filter within the PLL circuit is periodically sampled and encoded using an ADC (analog to digital converter) circuit. In a second mode of operation, the circuit under test is initially not connected to the PLL circuit, but the input oscillator is initially so connected. When the circuit under test is connected, transient behavior is caused, which is again recorded using the ADC. In either case, codes generated by the ADC circuit are read by the processor of a computing system for comparison with codes similarly generated using a circuit known not to have fault conditions.
摘要翻译： PLL（锁相环）电路用于测试电路设备中的各个电路的装置中。 当该振荡器连接到PLL电路内的相位比较器的输入之一时，PLL电路以由输入振荡器的输出提供的输入频率工作。 当不进行这种连接时，PLL电路以自适应频率工作，该频率通过将被测电路与存在于PLL电路中的压控振荡器内的频率控制节点连接而变化。 在第一种工作模式下，被测电路最初连接到频率控制节点，但是输入振荡器没有连接到相位比较器。 当输入振荡器如此连接时，振荡频率从与被测电路相关联的自适应频率移动到输入频率。 在这种瞬态行为期间，PLL电路内的环路滤波器的输出使用ADC（模数转换器）电路进行定期采样和编码。 在第二种工作模式下，被测电路最初不连接到PLL电路，但是输入振荡器最初是连接的。 当被测电路连接时，会引起瞬态行为，再次使用ADC进行记录。 在这两种情况下，由ADC电路产生的代码由计算系统的处理器读取，以便与使用已知不具有故障条件的电路类似地生成的代码进行比较。
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