公开(公告)号：USD659848S1

公开(公告)日：2012-05-15

申请号：US29390267

申请日：2011-04-22

申请人： Joel TerMaat ,  Matthew Robert Kreifels ,  Hendrik Viljoen ,  Scott Whitney

设计人： Joel TerMaat ,  Matthew Robert Kreifels ,  Hendrik Viljoen ,  Scott Whitney

公开(公告)号：US20060141554A1

公开(公告)日：2006-06-29

申请号：US10966536

申请日：2004-10-14

申请人： Kyle Gee ,  Courtenay Hart ,  Richard Haugland ,  Wayne Patton ,  Scott Whitney

发明人： Kyle Gee ,  Courtenay Hart ,  Richard Haugland ,  Wayne Patton ,  Scott Whitney

IPC分类号： G01N33/48 ,  C07F15/04

CPC分类号： C07D263/62 ,  A61K49/0021 ,  A61K49/0039 ,  A61K49/0041 ,  A61K49/0052 ,  C07D311/12 ,  C07D311/16 ,  C07D311/18 ,  C07D405/14 ,  C07F5/022 ,  G01N1/30 ,  G01N33/533 ,  G01N33/582

摘要： The present invention provides methods and fluorescent compounds that facilitate detecting and labeling of a fusion protein by being capable of selectively binding to an affinity tag. The fluorescent compounds have the general formula A(B)n, wherein A is a fluorophore, B is a binding domain that is a charged chemical moiety, a protein or fragment thereof and n is an integer from 1-6 with the proviso that the protein or fragment thereof not be an antibody or generated from an antibody. The present invention provides specific fluorescent compounds and methods used to detect and label fusion proteins that contain a poly-histidine affinity tag. These compounds have the general formula A(L)m(B)n wherein A is a fluorophore, L is a linker, B is an acetic acid binding domain, m is an integer from 1 to 4 and n is an integer from 1 to 6. The acetic acid groups interact directly with the positively charged histidine residues of the affinity tag to effectively label and detect a fusion protein containing such an affinity tag when present in an acidic or neutral environment.

公开(公告)号：US06980440B2

公开(公告)日：2005-12-27

申请号：US10642110

申请日：2003-08-15

申请人： Mathew A. Nieman ,  Doreen DePalma Burns ,  John Scott Whitney

发明人： Mathew A. Nieman ,  Doreen DePalma Burns ,  John Scott Whitney

IPC分类号： H05K7/14 ,  H05K7/20 ,  H05K7/18

CPC分类号： H05K7/20563 ,  H05K7/1418

摘要： A card guide is used in guiding a circuit board with respect to a chassis. The card guide includes a guide rail extending along the card guide in a first direction, an end portion configured for removably attaching the card guide to the chassis, and a finger extending in a second direction. The finger has a shape and size to allow interconnection with an adjacent card guide. The finger defines an endpoint of a space allowing airflow in a third direction past the card guide.

摘要翻译： 卡引导件用于相对于底盘引导电路板。 卡引导件包括沿着第一方向沿着卡引导件延伸的导轨，构造成用于将卡引导件可拆卸地附接到底架的端部和沿第二方向延伸的手指。 手指具有形状和尺寸以允许与相邻卡片导板的互连。 手指定义了一个空间的端点，允许沿第三方向的气流通过卡片导板。

公开(公告)号：US20050034989A1

公开(公告)日：2005-02-17

申请号：US10861787

申请日：2004-06-04

申请人： Roumen Bogoev ,  Scott Whitney ,  Joseph Amshey

发明人： Roumen Bogoev ,  Scott Whitney ,  Joseph Amshey

IPC分类号： G01N33/48 ,  C07K1/34 ,  C12M1/00 ,  C12M1/33 ,  C12N15/09 ,  C12Q1/68 ,  G01N1/10 ,  G01N1/28 ,  G01L1/20

CPC分类号： C07K1/34 ,  Y10T436/25375 ,  Y10T436/255 ,  Y10T436/2575

摘要： An apparatus and method for mincing a gel includes a gel mincing tube and a mesh material. The mesh material extends across the end of the tube. To subdivide a gel using the mincing apparatus, a gel is placed upon the mesh material in the mincing tube, the mincing tube, mesh material and the gel are spun in a centrifuge, forcing the gel through the mesh material so that the gel is subdivided into generally uniform smaller fragments. The mesh material may be secured to a tube in the form of a nesting tube. The nesting tube nests within the opening of a recovery vessel. The mesh material may be placed in series with a conditionally porous membrane in the nesting tube. Centrifuging the nesting tube and the recovery vessel subdivides gel material into fragments by forcing the gel through the mesh material. The gel subsequently falls upon the membrane, and may be treated on the membrane to extract or otherwise treat analytes in the gel material.

摘要翻译： 用于切割凝胶的设备和方法包括凝胶切割管和网状材料。 网状材料延伸穿过管的端部。 为了使用切碎装置对凝胶进行细分，将凝胶放置在打孔管中的网状材料上，在离心机中将切细管，网状材料和凝胶纺丝，迫使凝胶通过网状材料，使凝胶细分 变成大致均匀的较小碎片。 网状材料可以以嵌套管的形式固定到管。 嵌套管嵌套在回收容器的开口内。 网状材料可以与嵌套管中的条状多孔膜串联放置。 将嵌套管和回收容器离心通过使凝胶通过网状材料将凝胶材料细分成碎片。 凝胶随后落在膜上，并且可以在膜上处理以提取或以其它方式处理凝胶材料中的分析物。

公开(公告)号：US06635489B2

公开(公告)日：2003-10-21

申请号：US09988746

申请日：2001-11-20

申请人： Scott Whitney

发明人： Scott Whitney

IPC分类号： G01N3368

CPC分类号： G01N33/542 ,  C12Q1/68 ,  G01N1/30 ,  G01N27/44721 ,  G01N27/44726 ,  Y10S435/81 ,  Y10T436/10 ,  Y10T436/143333 ,  Y10T436/24 ,  Y10T436/25 ,  C12Q2565/125 ,  C12Q2563/173 ,  C12Q2527/125

摘要： Methods for detecting biopolymers in a matrix are disclosed, which involve contacting the matrix with a sensitizing reagent, which may include one or more optionally substituted heteroaromatic compounds; contacting the matrix with one or more reduceable metal salts to stain the biopolymer; and detecting the stained biopolymer. Also disclosed are compositions for carrying out the invention and compositions made according to the invention. Also disclosed are kits for carrying out the methods of the invention.

摘要翻译： 公开了用于检测基质中生物聚合物的方法，其涉及将基质与敏化试剂接触，敏化试剂可以包括一种或多种任选取代的杂芳族化合物; 使基质与一种或多种可还原金属盐接触以染色生物聚合物; 并检测染色的生物聚合物。 还公开了用于实施本发明的组合物和根据本发明制备的组合物。 还公开了用于实施本发明的方法的试剂盒。

公开(公告)号：US06269435B1

公开(公告)日：2001-07-31

申请号：US09152944

申请日：1998-09-14

申请人： William J. Dally ,  Scott Whitney Rixner ,  John Owens ,  Ujval J. Kapasi

发明人： William J. Dally ,  Scott Whitney Rixner ,  John Owens ,  Ujval J. Kapasi

IPC分类号： G06F9305

CPC分类号： G06F9/3885 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/3012 ,  G06F9/3828 ,  G06F9/3842 ,  G06F9/3879 ,  G06F9/3891 ,  G06F15/8084

摘要： A processor implements conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full processor efficiency without cycles wasted due to branch latency. Data to be processed is divided into two groups based on whether or not they satisfy a given condition by, e.g., steering each to one of two index vectors. Once the data has been segregated in this way, subsequent processing can be performed without conditional operations, processor cycles wasted due to branch latency, incorrect speculation or execution of unnecessary instructions due to predication.

摘要翻译： 处理器实现条件向量操作，其中基于条件向量将包含要在条件操作中使用的多个操作数的输入向量划分为两个或更多个输出向量。 然后可以以全处理器效率处理每个输出向量，而不会由于分支延迟而浪费周期。 基于它们是否满足给定条件，待处理的数据被分成两组，例如通过将其转换为两个索引向量中的一个。 一旦以这种方式隔离了数据，可以执行后续处理，而无需条件操作，由于分支延迟浪费处理器周期，由于预测导致不正确的推测或不必要的指令的执行。

公开(公告)号：US06233191B1

公开(公告)日：2001-05-15

申请号：US09510326

申请日：2000-02-22

申请人： Scott Whitney Gould ,  Joseph Andrew Iadanza ,  Frank Ray Keyser, III

发明人： Scott Whitney Gould ,  Joseph Andrew Iadanza ,  Frank Ray Keyser, III

IPC分类号： G11C700

CPC分类号： G06F7/785 ,  G06F5/10 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/12 ,  G11C8/00 ,  H03K19/17704 ,  H03K19/1776

摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

摘要翻译： 提供具有多个子阵列的现场可编程存储器阵列。 提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。 这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。 公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。

公开(公告)号：US5949719A

公开(公告)日：1999-09-07

申请号：US190905

申请日：1998-11-12

申请人： Kim P. N. Clinton ,  Scott Whitney Gould ,  Joseph Andrew Iadanza ,  Frank Ray Keyser, III ,  Ralph David Kilmoyer ,  Michael Joseph Laramie ,  Victor Paul Seidel ,  Terrance John Zittritsch

发明人： Kim P. N. Clinton ,  Scott Whitney Gould ,  Joseph Andrew Iadanza ,  Frank Ray Keyser, III ,  Ralph David Kilmoyer ,  Michael Joseph Laramie ,  Victor Paul Seidel ,  Terrance John Zittritsch

IPC分类号： G06F5/10 ,  G06F7/78 ,  G11C5/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/12 ,  G11C8/00 ,  H03K19/177 ,  G11C13/00

CPC分类号： G06F7/785 ,  G06F5/10 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/12 ,  G11C8/00 ,  H03K19/17704 ,  H03K19/1776

摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

公开(公告)号：US5748009A

公开(公告)日：1998-05-05

申请号：US707840

申请日：1996-09-09

申请人： Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

发明人： Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/1737

摘要： A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g., clock) input available to at least one of the input multiplexers; a flip-flop connected within the logic cell; and internal cell feedback. The preferred method of programming utilizes user-programmed SRAM memory cells.

摘要翻译： 可编程逻辑单元具有四个逻辑门，其中两个可配置。 两个可配置逻辑门位于逻辑单元输入附近。 每个可配置逻辑门具有两个输入，每个输入连接到四个逻辑单元输入之一。 剩余的两个逻辑门接收可配置逻辑门的输出。 提供四个独立的逻辑单元输入节点，每个具有与可编程输入多路复用器相关联的逻辑单元输入节点。 每个输入多路复用器可以具有连接到至少两种类型的互连导体的输入。 该单元还具有两个输出路径，每个输出路径与其相关联，具有独立控制的输出多路复用器。 每个输出多路复用器的输出连接到另一个输出多路复用器的输入端。 附加特征包括具有连接到两个单元输入节点的输入的多路复用器，连接到第三逻辑单元输入节点的选择输入和连接到单元输出节点的输出; 用于至少一个输入多路复用器的系统低偏移数据（例如，时钟）输入; 连接在逻辑单元内的触发器; 和内部单元反馈。 优选的编程方法利用用户编程的SRAM存储单元。

公开(公告)号：US5732246A

公开(公告)日：1998-03-24

申请号：US480639

申请日：1995-06-07

申请人： Scott Whitney Gould ,  Frank Ray Keyser, III ,  Wendell Ray Larsen ,  Brian Allen Worth

发明人： Scott Whitney Gould ,  Frank Ray Keyser, III ,  Wendell Ray Larsen ,  Brian Allen Worth

IPC分类号： H03K19/173 ,  G01R31/3185 ,  H03K3/037 ,  H03K19/177 ,  G06F9/455 ,  G06F17/50

CPC分类号： G01R31/318519 ,  H03K19/17704 ,  H03K19/17748 ,  H03K3/0375

摘要： A given interconnect of a programmable gate array includes a programmable repeater circuit that enables selective isolation and testing of a select block of configured circuitry within the programmable gate array. The programmable repeater circuit includes an input node coupled to a first portion of the given interconnect and an output node coupled to a second portion of the given interconnect. A selective buffer circuit selectively outputs a buffered output signal to the output node that is related to a logic state at the input node. A signal storage circuit is also connected to the input node for selectively storing the logic state received from the input node. In a further embodiment, the signal storage circuit comprises an LSSD register. A primary latch of the LSSD register receives data selectively either from the input node, in accordance with a first clock signal, or alternatively from a secondary serial input node, in accordance with a second clock signal. A secondary latch of the LSSD register is selectively coupled, per a third clock signal, to receive and latch therein latched data of the primary latch. Data representative of data latched within the secondary latch is provided at a secondary serial output, and selectively provided at the primary output node when enabled per a programmable enable signal. In yet a further embodiment, the LSSD register is part of a serial scan chain for selectively interfacing an interconnect boundary of the select block of the configured circuitry within the programmable gate array.

摘要翻译： 可编程门阵列的给定互连包括可编程中继器电路，其实现对可编程门阵列内的配置电路的选择块的选择性隔离和测试。 可编程中继器电路包括耦合到给定互连的第一部分的输入节点和耦合到给定互连的第二部分的输出节点。 选择性缓冲电路有选择地将缓冲的输出信号输出到与输入节点处的逻辑状态相关的输出节点。 信号存储电路也连接到输入节点，用于选择性地存储从输入节点接收的逻辑状态。 在另一实施例中，信号存储电路包括LSSD寄存器。 根据第二时钟信号，LSSD寄存器的主锁存器根据第一时钟信号，或者备选地从辅助串行输入节点选择性地从输入节点接收数据。 每个第三时钟信号选择性地耦合LSSD寄存器的辅助锁存器，以在其中接收并锁存主锁存器的锁存数据。 在辅助锁存器中锁存的数据的数据被提供在次级串行输出端，并且当每个可编程使能信号使能时，被选择地提供在主输出节点处。 在又一个实施例中，LSSD寄存器是串行扫描链的一部分，用于选择性地接合可编程门阵列内的配置电路的选择块的互连边界。