公开(公告)号：US20050208756A1

公开(公告)日：2005-09-22

申请号：US11052987

申请日：2005-02-09

Applicant: Atsushi Matsushita ,  Isao Matsumoto ,  Kazuaki Inukai ,  Hong Shin ,  Naofumi Ohashi ,  Shuji Sone ,  Kaori Misawa

Inventor： Atsushi Matsushita ,  Isao Matsumoto ,  Kazuaki Inukai ,  Hong Shin ,  Naofumi Ohashi ,  Shuji Sone ,  Kaori Misawa

IPC: H01L21/3065 ,  G03F7/42 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC classification number: G03F7/427 ,  H01L21/0274 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7681

Abstract: Disclosed is a method of removing resist preventing increase of dielectric constant of low permittivity insulating films and preventing remains of resist. Using a resist mask, a protection insulating film, a MSQ film, and a silicon oxide film composing an ILD are RIE dry etched sequentially, and a via is formed on the surface of a substrate for processing reaching the diffusion layer on the substrate for processing. Subsequent process consists of; removing a modified layer formed on the substrate for processing surface because of prior etching using plasma gas by plasma excitation of NH3 gas, and another etching for complete removal of the resist mask by irradiation of hydrogen active species created by hydrogen gas and inert gas, of which example is helium gas or argon gas.

Abstract translation: 公开了一种去除抗蚀剂的方法，该方法防止低介电常数绝缘膜的介电常数增加并防止抗蚀剂残留。 使用抗蚀剂掩模，保护绝缘膜，MSQ膜和构成ILD的氧化硅膜，依次进行RIE干式蚀刻，并且在用于处理的基板的表面上形成通孔以到达用于处理的基板上的扩散层 。 随后的过程包括 由于通过等离子体激发NH 3气体的等离子体气体的先前蚀刻，除去形成在用于处理表面的基板上的改性层，以及通过产生氢活性物质的照射完全除去抗蚀剂掩模的另一蚀刻 通过氢气和惰性气体，例如氦气或氩气。

公开(公告)号：US20050170102A1

公开(公告)日：2005-08-04

申请号：US11036138

申请日：2005-01-18

Applicant: Isao Matsumoto ,  Naofumi Ohashi ,  Kaori Misawa ,  Shuji Sone

Inventor： Isao Matsumoto ,  Naofumi Ohashi ,  Kaori Misawa ,  Shuji Sone

IPC: H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H05H1/00

CPC classification number: H01L21/02137 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835

Abstract: A method for manufacturing a semiconductor device comprises: exposing a surface of a substrate to plasma; and forming an insulating film containing a low dielectric constant material on the surface of the substrate. A method for manufacturing a semiconductor device comprises: forming a modified layer by exposing a surface of a substrate to plasma; and forming an insulating film containing a low dielectric constant material on the modified layer. A method for manufacturing a semiconductor device comprises: forming an adhesion enhancement layer on a substrate; exposing a surface of the adhesion enhancement layer to plasma; and forming a first insulating film on the adhesion enhancement layer.

Abstract translation: 一种制造半导体器件的方法包括：将衬底的表面暴露于等离子体; 以及在所述基板的表面上形成含有低介电常数材料的绝缘膜。 一种制造半导体器件的方法包括：通过将衬底的表面暴露于等离子体来形成改性层; 以及在所述改性层上形成含有低介电常数材料的绝缘膜。 一种制造半导体器件的方法包括：在衬底上形成粘合增强层; 将粘附增强层的表面暴露于等离子体; 以及在所述粘合增强层上形成第一绝缘膜。

公开(公告)号：US6150684A

公开(公告)日：2000-11-21

申请号：US317857

申请日：1999-05-25

Applicant: Shuji Sone

Inventor： Shuji Sone

IPC: H01L27/04 ,  H01L21/314 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/92 ,  H01L29/76

CPC classification number: H01L21/02274 ,  H01L21/02197 ,  H01L21/02356 ,  H01L21/31691 ,  H01L28/40

Abstract: A thin-film capacitor having a perovskite-structured polycrystalline oxide thin-film as its dielectric, that exhibits an excellent insulation property is provided. This capacitor comprises a perovskite-structured, polycrystalline oxide thin-film, and top and bottom electrodes located at each side of the thin-film The perovskite-structured, polycrystalline oxide thin-film has a general formula of ABO.sub.3, where A is at least one element selected from the group consisting of bivalent metallic elements, lead, and lanthanum, and B is at least one element selected from the group consisting of quadrivalent metallic elements. A ratio of (A/B) is in a range from 1.1 to 2.0. The oxide thin-film has granular crystal grains. The perovskite-structured, polycrystalline oxide thin-film is formed by forming a perovskite-structured, amorphous oxide thin-film and by crystallizing the perovskite-structured, amorphous oxide thin-film due to heat treatment.

Abstract translation: 提供具有优异绝缘性的具有钙钛矿结构的多晶氧化物薄膜作为电介质的薄膜电容器。 该电容器包括钙钛矿结构的多晶氧化物薄膜，以及位于薄膜两侧的顶部和底部电极。钙钛矿结构的多晶氧化物薄膜具有通式ABO 3，其中A至少为 选自二价金属元素，铅和镧的一种元素，B是选自四价金属元素中的至少一种元素。 （A / B）的比例在1.1至2.0的范围内。 氧化物薄膜具有颗粒状晶粒。 钙钛矿结构的多晶氧化物薄膜是通过形成钙钛矿结构的无定形氧化物薄膜，并且通过结晶由于热处理而产生的钙钛矿结构的无定形氧化物薄膜而形成的。

公开(公告)号：US07538038B2

公开(公告)日：2009-05-26

申请号：US11052987

申请日：2005-02-09

Applicant: Atsushi Matsushita ,  Isao Matsumoto ,  Kazuaki Inukai ,  Hong Jae Shin ,  Naofumi Ohashi ,  Shuji Sone ,  Kaori Misawa

Inventor： Atsushi Matsushita ,  Isao Matsumoto ,  Kazuaki Inukai ,  Hong Jae Shin ,  Naofumi Ohashi ,  Shuji Sone ,  Kaori Misawa

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/461 ,  H01L21/47

CPC classification number: G03F7/427 ,  H01L21/0274 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7681

Abstract: Disclosed is a method of removing resist preventing increase of dielectric constant of low permittivity insulating films and preventing remains of resist. Using a resist mask, a protection insulating film, a MSQ film, and a silicon oxide film composing an ILD are RIE dry etched sequentially, and a via is formed on the surface of a substrate for processing reaching the diffusion layer on the substrate for processing. Subsequent process consists of; removing a modified layer formed on the substrate for processing surface because of prior etching using plasma gas by plasma excitation of NH3 gas, and another etching for complete removal of the resist mask by irradiation of hydrogen active species created by hydrogen gas and inert gas, of which example is helium gas or argon gas.

Abstract translation: 公开了一种去除抗蚀剂的方法，该方法防止低介电常数绝缘膜的介电常数增加并防止抗蚀剂残留。 使用抗蚀剂掩模，保护绝缘膜，MSQ膜和构成ILD的氧化硅膜，依次进行RIE干式蚀刻，并且在用于处理的基板的表面上形成通孔以到达用于处理的基板上的扩散层 。 随后的过程包括 由于使用等离子体气体等离子体激发NH 3气体进行的先前的蚀刻，除去形成在基板上用于处理表面的改性层，以及通过氢气和惰性气体产生的氢活性物质的照射完全除去抗蚀剂掩模的另一种蚀刻 例如氦气或氩气。

公开(公告)号：US06323057B1

公开(公告)日：2001-11-27

申请号：US09635174

申请日：2000-08-09

Applicant: Shuji Sone

Inventor： Shuji Sone

IPC: H01L218242

CPC classification number: H01L21/02274 ,  H01L21/02197 ,  H01L21/02356 ,  H01L21/31691 ,  H01L28/40

Abstract: A thin-film capacitor having a perovskite-structured polycrystalline oxide thin-film as its dielectric, that exhibits an excellent insulation property is provided. This capacitor comprises a perovskite-structured, polycrystalline oxide thin-film, and top and bottom electrodes located at each side of the thin-film. The perovskite-structured, polycrystalline oxide thin-film has a general formula of ABO3, where A is at least one element selected from the group consisting of bivalent metallic elements, lead, and lanthanum, and B is at least one element selected from the group consisting of quadrivalent metallic elements. A ratio of (A/B) is in a range from 1.1 to 2.0. The oxide thin-film has granular crystal grains. The perovskite-structured, polycrystalline oxide thin-film is formed by forming a perovskite-structured, amorphous oxide thin-film and by crystallizing the perovskite-structured, amorphous oxide thin-film due to heat treatment.

Abstract translation: 提供具有优异绝缘性的具有钙钛矿结构的多晶氧化物薄膜作为电介质的薄膜电容器。 该电容器包括钙钛矿结构的多晶氧化物薄膜，以及位于薄膜两侧的顶部和底部电极。 钙钛矿结构的多晶氧化物薄膜具有ABO 3的通式，其中A是选自二价金属元素，铅和镧中的至少一种元素，B是选自以下的至少一种元素： 由四价金属元素组成。 （A / B）的比例在1.1至2.0的范围内。 氧化物薄膜具有颗粒状晶粒。 钙钛矿结构的多晶氧化物薄膜是通过形成钙钛矿结构的无定形氧化物薄膜，并且通过结晶由于热处理而产生的钙钛矿结构的无定形氧化物薄膜而形成的。

公开(公告)号：US20060003577A1

公开(公告)日：2006-01-05

申请号：US11037163

申请日：2005-01-19

Applicant: Shuji Sone

Inventor： Shuji Sone

IPC: H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76844

Abstract: To effectively reduce the dielectric constant of an interlayer insulation film including a low dielectric constant film of a porous structure, and easily realize a practical application of a semiconductor device having an ultrafine and highly reliable Damascene wiring structure. A first interlayer insulation film including a porous first low dielectric constant film is formed on a lower layer wiring, and a first side wall metal is formed on a side wall of a via hole arranged in the first low dielectric constant film, and thereafter a first etching stopper layer is etched and the lower layer wiring is exposed. Then, a via plug is embedded into the via hole. In the same manner, after a second side wall metal is arranged on a side wall of a trench in a second interlayer insulation film including a porous second low dielectric constant film, a second etching stopper layer is etched, and an upper layer wiring that connects to the via plug is formed.

Abstract translation: 为了有效地降低包括多孔结构的低介电常数膜的层间绝缘膜的介电常数，并且容易实现具有超细且高可靠性的大马士革布线结构的半导体器件的实际应用。 在下层布线上形成包括多孔第一低介电常数膜的第一层间绝缘膜，在布置在第一低介电常数膜中的通孔的侧壁上形成第一侧壁金属， 蚀刻阻挡层被蚀刻并且下层布线被暴露。 然后，通孔插入到通孔中。 以相同的方式，在包括多孔第二低介电常数膜的第二层间绝缘膜中在沟槽的侧壁上布置第二侧壁金属之后，蚀刻第二蚀刻停止层，并且连接上层布线 形成通孔塞。

公开(公告)号：US20050199586A1

公开(公告)日：2005-09-15

申请号：US11052911

申请日：2005-02-09

Applicant: Atsushi Matsushita ,  Isao Matsumoto ,  Kazuaki Inukai ,  Hong Shin ,  Naofumi Ohashi ,  Shuji Sone ,  Kaori Misawa

Inventor： Atsushi Matsushita ,  Isao Matsumoto ,  Kazuaki Inukai ,  Hong Shin ,  Naofumi Ohashi ,  Shuji Sone ,  Kaori Misawa

IPC: H01L21/3065 ,  B44C1/22 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/31138 ,  G03F7/427 ,  H01J37/32192 ,  H01J37/32357 ,  H01J37/32477 ,  H01J2237/3342

Abstract: In resist removal using hydrogen gas, the specific dielectric constant of an insulating film of a low dielectric constant can be reduced and the resist removal speed can be increased. A wafer is loaded on a rotary table in a chamber, and hydrogen mixed gas is introduced into a discharge tube from a gas introduction port, and a μ wave is supplied into the discharge tube via a waveguide, and the mixed gas is excited by plasma, and a hydrogen active species is generated. And, a neutral radical (hydrogen radical) of hydrogen atoms or hydrogen molecules is introduced into the chamber from a gas transport pipe and a resist mask on the surface of the wafer is removed. Here, by a substrate heating system for heating the rotary table and controlling the temperature, the temperature of the wafer is set within the range from 200° C. to 400° C. The processed gas after resist removal is ejected from the chamber through a gas ejection port by an exhaust system.

Abstract translation: 在使用氢气的抗蚀剂去除中，可以降低介电常数低的绝缘膜的比介电常数，并且可以提高抗蚀剂去除速度。 将晶片装载在室内的旋转台上，将氢气混合气体从气体导入口引入放电管，经由波导将mu波供给到放电管内，混合气体被等离子体激发 ，生成氢活性物质。 并且，从气体输送管将氢原子或氢分子的中性自由基（氢基团）引入到室中，并且去除晶片表面上的抗蚀剂掩模。 这里，通过用于加热旋转台并控制温度的基板加热系统，将晶片的温度设定在200℃至400℃的范围内。抗蚀剂除去后的处理气体通过一个 气体排出口由排气系统。

公开(公告)号：US06632738B2

公开(公告)日：2003-10-14

申请号：US09876207

申请日：2001-06-06

Applicant: Shuji Sone

Inventor： Shuji Sone

IPC: H01L2144

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76859 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interlayer insulating film and a first via connected to a diffusion layer in a MOS transistor are formed on the diffusion layer. Then, a low dielectric constant film for a first layer copper interconnection, and the first layer copper interconnection connected to the first via are formed. Then, an etching stopper film, an interlayer insulating film, and a low dielectric constant film for a second layer copper interconnection are formed in this order. Then, a via hole is formed in the etching stopper film and the interlayer insulating film, and a groove is formed in the low dielectric constant film for the second layer copper interconnection. A barrier metal layer is then formed. Thereafter, Ar ions are implanted. At the time, the implantation energy is 50 keV, and the dose is 1×1017 cm−2. A second via and the second layer copper interconnection are formed, and annealing is performed at a temperature of 400° C.

Abstract translation: 在扩散层上形成层间绝缘膜和连接到MOS晶体管中的扩散层的第一通孔。 然后，形成用于第一层铜互连的低介电常数膜和连接到第一通孔的第一层铜互连。 然后，依次形成蚀刻停止膜，层间绝缘膜和用于第二层铜互连的低介电常数膜。 然后，在蚀刻停止膜和层间绝缘膜中形成通孔，并且在用于第二层铜互连的低介电常数膜中形成沟槽。 然后形成阻挡金属层。 此后，植入Ar离子。 此时，植入能量为50keV，剂量为1×10 17 HIL> < - 2 。 形成第二通孔和第二层铜互连，并在400℃的温度下进行退火。

公开(公告)号：US06184044B2

公开(公告)日：2001-02-06

申请号：US09208411

申请日：1998-12-10

Applicant: Shuji Sone ,  Yoshitake Kato

Inventor： Shuji Sone ,  Yoshitake Kato

IPC: H01L2100

CPC classification number: H01L28/56 ,  H01L21/31691

Abstract: The present invention relates to a thin film capacitor that may be used as a stacked capacitor in a memory cell. In a thin film capacitor including a high dielectric constant layer sandwiched by two electrode layers, the high dielectric constant layer includes at least one perovskite-type oxide layer having a columnar structure and at least one perovskite-type oxide layer having a granular structure.

Abstract translation: 薄膜电容器本发明涉及可用作存储单元中堆叠电容器的薄膜电容器。 在包含由两个电极层夹着的高介电常数层的薄膜电容器中，高介电常数层包括具有柱状结构的至少一种钙钛矿型氧化物层和至少一种具有颗粒结构的钙钛矿型氧化物层。

公开(公告)号：US06504228B1

公开(公告)日：2003-01-07

申请号：US09611065

申请日：2000-07-06

Applicant: Shuji Sone

Inventor： Shuji Sone

IPC: H01L2900

CPC classification number: H01L28/75 ,  H01L28/55

Abstract: A lower electrode film is made to have a crystal grain laminated structure composed of a granular structure crystal grain layer and a columnar structure crystal grain layer. Also, a barrier layer is formed to be a granular structure crystal grain layer made of tantalum nitride containing 10 atm % or more and 50 atm % or less of nitrogen. Thereby, a semiconductor device comprising electrode films wherein both favorable oxygen barrier performance and current conductivity are compatible can be provided.

Abstract translation: 使下电极膜具有由粒状结构晶粒层和柱状结构晶粒层构成的晶粒层叠结构。 另外，阻挡层形成为由含有10atm％以上且50atm％以下的氮的氮化钽制成的粒状结构晶粒层。 因此，可以提供包括电极膜的半导体器件，其中有利的氧气阻隔性能和电流传导性都兼容。