公开(公告)号：US08575668B2

公开(公告)日：2013-11-05

申请号：US13116416

申请日：2011-05-26

申请人： William F. Clark, Jr. ,  Stephen E. Luce

发明人： William F. Clark, Jr. ,  Stephen E. Luce

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L28/40 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/13

摘要： A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate.

公开(公告)号：US20130119490A1

公开(公告)日：2013-05-16

申请号：US13294610

申请日：2011-11-11

申请人： David L. HARAME ,  Stephen E. LUCE ,  Anthony K. STAMPER

发明人： David L. HARAME ,  Stephen E. LUCE ,  Anthony K. STAMPER

IPC分类号： H01L29/84 ,  G06F17/50 ,  H01L21/02

CPC分类号： H01L41/083 ,  G06F17/5068 ,  H01L21/84 ,  H01L27/1203 ,  H01L41/081 ,  H01L41/094 ,  H01L41/332 ,  H03H3/02 ,  H03H9/1007 ,  H03H9/173 ,  H03H2001/0064 ,  H03H2003/027 ,  H03H2009/155

摘要： Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam from a silicon layer on an insulator. The method further includes providing a coating of insulator material over the single crystalline beam. The method further includes forming a via through the insulator material. The method further includes providing a sacrificial material in the via and over the insulator material. The method further includes providing a lid on the sacrificial material. The method further includes providing further sacrificial material in a trench of a lower wafer. The method further includes bonding the lower wafer to the insulator, under the single crystalline beam. The method further includes venting the sacrificial material and the further sacrificial material to form an upper cavity above the single crystalline beam and a lower cavity, below the single crystalline beam.

摘要翻译： 提供了与CMOS器件集成的体声波滤波器和/或体声波谐振器，制造方法和设计结构。 该方法包括从绝缘体上的硅层形成单晶束。 该方法还包括在单晶束上提供绝缘体材料涂层。 该方法还包括通过绝缘体材料形成通孔。 该方法还包括在通孔和绝缘体材料上提供牺牲材料。 该方法还包括在牺牲材料上提供盖子。 该方法还包括在下晶片的沟槽中提供另外的牺牲材料。 该方法还包括在单晶束下将下晶片接合到绝缘体。 该方法还包括排出牺牲材料和另外的牺牲材料，以在单晶束之下形成单结晶束上方的上空腔和在单晶束下方的下腔。

公开(公告)号：US20090250772A1

公开(公告)日：2009-10-08

申请号：US12099175

申请日：2008-04-08

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7834 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/423 ,  H01L29/66575

摘要： A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

摘要翻译： 提供一种半导体结构和制造方法，更具体地说，具有身体接触的场效应晶体管及其制造方法。 该结构包括具有第一导电类型的凸起源极区域和延伸到器件主体的凸起源极区域下方的有源区域的器件。 有源区具有不同于第一导电类型的第二导电类型。 接触区域与有源区域电接触。 该方法包括在器件的有源区上形成凸起的源极区域，并形成与有源区域相同的导电类型的接触区域，其中有源区域在接触区域和器件的主体之间形成接触体。

公开(公告)号：US20090124047A1

公开(公告)日：2009-05-14

申请号：US12353549

申请日：2009-01-14

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC分类号： H01L21/70

CPC分类号： H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

摘要翻译： 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US20080088014A1

公开(公告)日：2008-04-17

申请号：US11528227

申请日：2006-09-26

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

摘要翻译： 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US07087997B2

公开(公告)日：2006-08-08

申请号：US09805027

申请日：2001-03-12

申请人： Lloyd G. Burrell ,  Edward E. Cooney, III ,  Jeffrey P. Gambino ,  John E. Heidenreich, III ,  Hyun Koo Lee ,  Mark D. Levy ,  Baozhen Li ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Anthony K. Stamper ,  Kwong Hon Wong ,  Sally J. Yankee

发明人： Lloyd G. Burrell ,  Edward E. Cooney, III ,  Jeffrey P. Gambino ,  John E. Heidenreich, III ,  Hyun Koo Lee ,  Mark D. Levy ,  Baozhen Li ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Anthony K. Stamper ,  Kwong Hon Wong ,  Sally J. Yankee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

公开(公告)号：US06504203B2

公开(公告)日：2003-01-07

申请号：US09681197

申请日：2001-02-16

申请人： Jeffrey P. Gambino ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Henry W. Trombley

发明人： Jeffrey P. Gambino ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Henry W. Trombley

IPC分类号： H01L29788

CPC分类号： H01L28/55 ,  H01L21/76838 ,  H01L23/5223 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： The present invention provides a method of forming a capacitor in a last metal wiring layer, and the structure so formed. The invention further provides a spacer formed around the capacitor to electrically isolate portions of the capacitor

摘要翻译： 本发明提供一种在最后一个金属布线层中形成电容器的方法以及如此形成的结构。 本发明还提供一种形成在电容器周围的隔离电路，以隔离电容器的部分

公开(公告)号：US5521434A

公开(公告)日：1996-05-28

申请号：US324203

申请日：1994-10-17

申请人： John E. Cronin ,  Stephen E. Luce ,  Steven H. Voldman

发明人： John E. Cronin ,  Stephen E. Luce ,  Steven H. Voldman

IPC分类号： H01L25/00 ,  H01L21/98 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18 ,  H01L23/528 ,  H01L23/538

CPC分类号： H01L25/50 ,  H01L23/535 ,  H01L25/0657 ,  H01L25/16 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A fabrication method and resultant electronic module having one or more surfaces enhanced with interconnects and components. Electronic modules having, for example, resistors and capacitors integral with a side surface thereof are disclosed. Further described are electronic modules with interconnects electrically attaching for example, side to side, or side to end surfaces are described. Moreover, discussion of an electronic module having a Silicon Front Face chip is contained herein. Specific details of the fabrication method, resulting electronic module, and related wafer processing are set forth.

摘要翻译： 具有通过互连和部件增强的一个或多个表面的制造方法和结果电子模块。 公开了具有例如与其侧表面成一体的电阻器和电容器的电子模块。 进一步描述了具有例如彼此电连接的互连件的电子模块，例如，侧向或侧向或端对端的表面。 此外，在此包含具有硅正面芯片的电子模块的讨论。 阐述了制造方法，所得到的电子模块和相关晶片处理的具体细节。

公开(公告)号：US20130119491A1

公开(公告)日：2013-05-16

申请号：US13294615

申请日：2011-11-11

申请人： Stephen E. LUCE ,  Anthony K. Stamper

发明人： Stephen E. LUCE ,  Anthony K. Stamper

IPC分类号： H01L29/84 ,  G06F9/45 ,  H01L21/02

CPC分类号： H03H9/02007 ,  G06F17/5072 ,  H01L21/84 ,  H01L27/1203 ,  H03H3/02 ,  H03H9/1007 ,  H03H9/173 ,  H03H2001/0064 ,  H03H2003/027 ,  H03H2009/155

摘要： Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS processes, methods of manufacture and design structures are disclosed. The method includes forming at least one beam comprising amorphous silicon material and providing an insulator material over and adjacent to the amorphous silicon beam. The method further includes forming a via through the insulator material and exposing a material underlying the amorphous silicon beam. The method further includes providing a sacrificial material in the via and over the amorphous silicon beam. The method further includes providing a lid on the sacrificial material and over the insulator material. The method further includes venting, through the lid, the sacrificial material and the underlying material to form an upper cavity above the amorphous silicon beam and a lower cavity below the amorphous silicon beam, respectively.

摘要翻译： 公开了与CMOS工艺，制造方法和设计结构集成的体声波滤波器和/或体声波谐振器。 该方法包括形成至少一个包含非晶硅材料的光束并在非晶硅光束上并邻近其提供绝缘体材料。 该方法还包括通过绝缘体材料形成通孔并暴露非晶硅束下面的材料。 该方法还包括在通孔和非晶硅光束上提供牺牲材料。 该方法还包括在牺牲材料上并在绝缘体材料之上提供盖子。 该方法还包括通过盖子排出牺牲材料和下面的材料，以分别在非晶硅束的上方形成上腔，并在非晶硅束的下方形成下腔。

公开(公告)号：US08211728B2

公开(公告)日：2012-07-03

申请号：US12632836

申请日：2009-12-08

申请人： Stephen E. Luce ,  Anthony K. Stamper

发明人： Stephen E. Luce ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： H01L21/76838 ,  H01H59/0009

摘要： A first dielectric material layer and a second dielectric material layer are formed on a substrate. Three conductive portions are formed within the second dielectric material layer. An optional third dielectric material layer and an optional dielectric capping layer may be formed over the three conductive portions. Portions of the second dielectric material layer and the first dielectric material layer are removed from within an area of a hole in a masking layer. The first dielectric material layer is laterally undercut to provide a micro-electro-mechanical-system (MEMS) switch comprising a conductive cantilever, a conductive plate, and a conductive actuator from the three conductive portions as portions of the first and second dielectric material layers are removed. The MEMS switch may be employed to provide mechanical switchable contact between the conductive cantilever and the conductive plate through an electrical signal on the conductive actuator.

摘要翻译： 第一介电材料层和第二电介质材料层形成在基板上。 在第二介电材料层内形成三个导电部分。 可以在三个导电部分上形成可选的第三介电材料层和可选的介电覆盖层。 第二介质材料层和第一介电材料层的一部分从掩模层中的孔的区域内被去除。 第一介电材料层被横向底切以提供微电子机械系统（MEMS）开关，其包括导电悬臂，导电板和导电致动器，作为第一和第二介电材料层的部分从三个导电部分 被删除。 MEMS开关可用于通过导电致动器上的电信号在导电悬臂与导电板之间提供机械可切换接触。