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    SYNTHESIZING GRAPHENE FROM METAL-CARBON SOLUTIONS USING ION IMPLANTATION
    1.
    发明申请
    SYNTHESIZING GRAPHENE FROM METAL-CARBON SOLUTIONS USING ION IMPLANTATION 有权
    使用离子植入法合成来自金属碳解决方案的石墨

    公开(公告)号：US20130026444A1

    公开(公告)日：2013-01-31

    申请号：US13647077

    申请日：2012-10-08

    申请人： BOARD OF REGENTS, THE UNIVERSITY OF TE ,  TEXAS INSTRUMENTS, INC.

    发明人： Luigi Colombo ,  Robert M. Wallace ,  Rodney S. Ruoff

    IPC分类号： H01L21/3115 ,  H01L21/311 ,  H01L29/15

    CPC分类号： H01L21/02612 ,  H01L21/02527

    摘要： A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.

    摘要翻译： 一种使用碳的离子注入合成石墨烯的方法和半导体器件。 使用离子注入将碳注入金属中。 在碳分布在金属中之后，对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。 然后将金属/石墨烯表面转移到电介质层，使得石墨烯层被放置在电介质层的顶部上。 然后去除金属层。 或者，凹陷区域被图案化并蚀刻在位于基底上的电介质层中。 金属后来形成在这些凹陷区域。 然后使用离子注入将碳注入到金属中。 然后可以对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。

    Reconfigurable optical add/drop multiplexer
    2.
    发明申请
    Reconfigurable optical add/drop multiplexer 有权
    可重配置的光分插复用器

    公开(公告)号：US20040047632A1

    公开(公告)日：2004-03-11

    申请号：US10236194

    申请日：2002-09-06

    申请人： Texas Instruments Inc.

    发明人： Donald Andrew Powell

    IPC分类号： H04J014/02 ,  G02B006/28

    CPC分类号： G02B6/29383 ,  G02B6/2931 ,  G02B6/29311 ,  G02B6/3512 ,  G02B6/356 ,  H04J14/0206 ,  H04J14/0212

    摘要： Disclosed is an add-drop multiplexer that receives an optical signal having a plurality of channels. The multiplexer spatially separates the channels, and a spatial light modulator within the multiplexer, which in some embodiments is a switched blazed grating, routes the channels along first or second paths according to whether the particular channels are to be sent along as a part of an output communication signal or nulldroppednull into a dropped-channel optical communications signal. The add-drop multiplexer is also operable to receive optical channels to be added to an optical signal and to use a spatial light modulator to add those optical signals to that optical signal.

    摘要翻译： 公开了一种接收具有多个信道的光信号的分插复用器。 多路复用器在空间上分离信道，并且多路复用器内的空间光调制器在一些实施例中是切换闪耀的光栅，根据特定信道是沿着第一路径还是第二路径沿着 输出通信信号或“丢弃”到丢弃信道光通信信号中。 分插复用器还可操作以接收要添加到光信号的光信道并使用空间光调制器将这些光信号添加到该光信号。

    Fast magneto-resistive head open and short detection for both voltage and current bias preamplifiers
    3.
    发明申请
    Fast magneto-resistive head open and short detection for both voltage and current bias preamplifiers 有权
    用于电压和电流偏置前置放大器的快速磁阻头开路和短路检测

    公开(公告)号：US20030053239A1

    公开(公告)日：2003-03-20

    申请号：US09952952

    申请日：2001-09-14

    申请人： Texas Instruments, Inc.

    发明人： Hong Jiang

    IPC分类号： G11B005/03 ,  G11B005/02

    CPC分类号： G11B5/455 ,  G11B5/012 ,  G11B19/04 ,  G11B2005/0016 ,  G11B2005/0018

    摘要： A circuit and method are presented for detecting a fault in a magneto-resistive head (18). The circuit includes a bias circuit (50) to produce a bias voltage across the head (18) and a pair of resistors (68,70) in series with the head (18) connected to the bias circuit (50) to carry a current (IVMR) from the bias circuit (50) in common with the head. A circuit (102,102null) is provided to determine a ratio of a voltage across the head (18) with respect to a voltage across the head (18) and the pair of resistors (68,70), and a circuit (104,106,104null,106null) is provided for indicating a fault if the ratio falls outside a predetermined range.

    摘要翻译： 提出了用于检测磁阻头（18）中的故障的电路和方法。 该电路包括偏置电路（50），以产生跨越头部（18）的偏置电压和与连接到偏置电路（50）的头部（18）串联的一对电阻器（68,70），以承载电流 （IVMR）与偏置电路（50）共用。 提供电路（102,102'）以确定头部（18）上的电压相对于头部（18）和一对电阻器（68,70）之间的电压的比率，以及电路（104,106,104'）， 106'）用于指示故障，如果该比值超出预定范围。

    Process to produce ultrathin crystalline silicon nitride on Si (111) for advanced gate dielectrics
    4.
    发明授权
    Process to produce ultrathin crystalline silicon nitride on Si (111) for advanced gate dielectrics 有权
    在Si（111）上生产用于先进栅极电介质的超薄晶体氮化硅的工艺

    公开(公告)号：US6420729B2

    公开(公告)日：2002-07-16

    申请号：US74796600

    申请日：2000-12-27

    申请人： TEXAS INSTRUMENTS INC

    发明人： WALLACE ROBERT M ,  WILK GLEN D ,  WEI YI ,  HATTANGADY SUNIL V

    IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/51 ,  H01L29/04

    CPC分类号： H01L29/513 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L27/1085 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66181

    摘要： A method of making a semiconductor device and the device. The device, according to a first embodiment, is fabricated by providing a silicon (111) surface, forming on the surface a dielectric layer of crystalline silicon nitride and forming an electrode layer on the dielectric layer of silicon nitride. The silicon (111) surface is cleaned and made atomically flat. The dielectric layer if formed of crystalline silicon nitride by placing the surface in an ammonia ambient at a pressure of from about 1x10-7 to about 1x10-5 Torr at a temperature of from about 850° C. to about 1000° C. The electrode layer is heavily doped silicon. According to a second embodiment, there is provided a silicon (111) surface on which is formed a first dielectric layer of crystalline silicon nitride having a thickness of about 2 monolayers. A second dielectric layer compatible with silicon nitride and having a higher dielectric constant than silicon nitride is formed on the first dielectric layer and an electrode layer is formed over the second dielectric layer. A third dielectric layer of silicon nitride having a thickness of about 2 monolayers can be formed between the second dielectric layer and the electrode layer. The second dielectric layer is preferably taken from the class consisting of tantalum pentoxide, titanium dioxide and a perovskite material. Both silicon nitride layers can be formed as in the first embodiment. The electrode layer is preferably heavily doped silicon

    摘要翻译： 制造半导体器件和器件的方法。 根据第一实施例的器件通过提供硅（111）表面来制造，在表面上形成结晶氮化硅的介电层并在氮化硅的介电层上形成电极层。 硅（111）表面被清洁并且原子地平坦。 如果由晶体氮化硅形成的电介质层，通过将表面放置在大约1×10-7至1×10-5乇的压力下，在大约850℃至大约1000℃的温度下。 层是重掺杂硅。 根据第二实施例，提供了一种硅（111）表面，在其上形成具有约2个单层厚度的结晶氮化硅的第一介电层。 与氮化硅相容并且具有比氮化硅更高的介电常数的第二电介质层形成在第一电介质层上，并且在第二电介质层上形成电极层。 可以在第二介电层和电极层之间形成具有约2个单层厚度的氮化硅的第三介电层。 第二电介质层优选取自五氧化二钽，二氧化钛和钙钛矿型材料。 可以如第一实施例那样形成氮化硅层。 电极层优选为重掺杂硅

    Reliable lamp life timer
    5.
    发明授权
    Reliable lamp life timer 有权
    可靠的灯泡使用寿命

    公开(公告)号：US6373201B2

    公开(公告)日：2002-04-16

    申请号：US74533200

    申请日：2000-12-21

    申请人： TEXAS INSTRUMENTS INC

    发明人： MORGAN DANIEL J ,  SMITH THOMAS E

    IPC分类号： H05B37/03 ,  G05F1/00

    CPC分类号： H05B37/03

    摘要： A method and apparatus for controlling a lamp. A timer (106) reads a rated safe life value from a memory (102) associated with a lamp in a lamp module (104). The memory (102) in the lamp module (104) contains a series of locations in which the rated safe life of the lamp has been stored, and a series of locations for storing the elapsed on time of the lamp. The timer controller (106) reads the series of locations storing the rated safe life of the lamp and verifies the validity of the values using a series of checksums and comparisons between the various values. The timer controller (106) also reads the series of locations storing the elapsed on time for the lamp and verifies the elapsed on time in a similar manner. If either the rated safe on time or the elapsed on time cannot be verified, the lamp is disabled. If both can be verified, and the lamp is enabled until the elapsed on time equals or exceeds the rated safe life.

    摘要翻译： 一种用于控制灯的方法和装置。 定时器（106）从与灯组件（104）中的灯相关联的存储器（102）读取额定​​安全寿命值。 灯模块（104）中的存储器（102）包含已经存储了灯的额定安全寿命的一系列位置，以及用于存储灯的经过时间的一系列位置。 定时器控制器（106）读取存储灯的额定安全寿命的一系列位置，并使用一系列校验和和各种值之间的比较来验证值的有效性。 定时器控制器（106）还读取存储灯的经过的一系列位置，并以类似的方式验证经过的时间。 如果无法验证额定安全启动时间或经过时间，则灯泡将被禁用。 如果两者都可以验证，并且灯已启用，直到经过的时间等于或超过额定安全寿命。

    Epitaxial cleaning process using HCL and N-type dopant gas to reduce defect density and auto doping effects
    6.
    发明授权
    Epitaxial cleaning process using HCL and N-type dopant gas to reduce defect density and auto doping effects 有权
    使用HCL和N型掺杂气体进行外延清洗工艺，以减少缺陷密度和自动掺杂效应

    公开(公告)号：US6274464B2

    公开(公告)日：2001-08-14

    申请号：US77142801

    申请日：2001-01-26

    申请人： TEXAS INSTRUMENTS INC

    发明人： DROBNY VLADIMIR F ,  BAO KEVIN X

    IPC分类号： H01L21/8249 ,  H01L21/20 ,  H01L21/36

    CPC分类号： H01L21/8249 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02661

    摘要： An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850° C. As the substrate is heated to a temperature of 1050° C., N+ dopant gas is injected into the carrier gas to suppress auto doping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080° C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080° C. Then an N-epitaxial layer is deposited on the second cap layer at 1080° C. The harmful effects of a dip in the dopant concentration profile at the bottoms of the collectors of the NPN transistors are avoided by the process.

    摘要翻译： 在P型硅衬底上形成外延层，其中多个P +掩埋层区域，多个N +掩埋层区域和占据衬底表面大部分的P +场层区域扩散。 将衬底装载在具有载气的反应器中。 衬底在大约850℃的温度下预烘烤。当衬底被加热到1050℃的温度时，N +掺杂剂气体被注入到载气中以抑制由于P +原子逸出的自由掺杂 P +埋层区域。 在N +掺杂气体的存在下，对基板进行高温烘烤循环。 第一薄的本征外延盖层沉积在衬底上，然后在1080℃下经受高温气体吹扫循环。然后将第二薄的本征外延盖层沉积在第一和第二高温气体吹扫 在1080℃下进行循环。然后在1080℃下在第二盖层上沉积N外延层。在NPN晶体管的集电极的底部的掺杂浓度分布中的浸渍的有害影响通过 的过程。