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公开(公告)号：US20110187002A1
公开(公告)日：2011-08-04
申请号：US13019509
申请日：2011-02-02
Applicant: Sadahiro Kishii , Tsuyoshi Kanki , Yoshihiro Nakata , Yasushi Kobayashi , Masato Tanaka , Akio Rokugawa
Inventor： Sadahiro Kishii , Tsuyoshi Kanki , Yoshihiro Nakata , Yasushi Kobayashi , Masato Tanaka , Akio Rokugawa
CPC classification number: H01L23/488 , H01L24/18 , H01L24/19 , H01L24/97 , H01L2224/04105 , H01L2224/24137 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/94 , H01L2224/97 , H01L2924/14 , H01L2924/15153 , H01L2924/15787 , H01L2924/15788 , H01L2224/82 , H01L2224/83 , H01L2924/00 , H01L2224/03
Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.
Abstract translation: 支撑基板包括位于第一表面的高度之上的第一表面和第二表面。 芯片安装在第一个表面上。 第一绝缘膜设置在每个芯片上。 第一导电插头连接到延伸穿过每个第一绝缘膜的芯片。 由树脂填充的填充材料填充芯片之间的空间。 布线布置在第一绝缘膜和用于互连不同芯片的填充材料之上。 第二表面，第一绝缘膜的上表面和填充材料的上表面位于同一水平。
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2.发明授权Method for manufacturing semiconductor device and polisher used in the method for manufacturing semiconductor device 有权用于制造半导体器件的方法的半导体器件和抛光机的制造方法公开(公告)号：US07842614B2
公开(公告)日：2010-11-30
申请号：US11968933
申请日：2008-01-03
Applicant: Tsuyoshi Kanki , Takahiro Kimura , Tetsuya Shirasu
Inventor： Tsuyoshi Kanki , Takahiro Kimura , Tetsuya Shirasu
IPC: H01L21/302 , H01L21/461 , B24B1/00 , C03C15/00
CPC classification number: H01L21/76816 , H01L21/3212 , H01L21/7684 , H01L21/76873
Abstract: A method for manufacturing a semiconductor device, including depositing an interconnect material including Cu or Cu alloy over an insulating film, and polishing the interconnect material by CMP with a polishing liquid, wherein the oxidation-reduction potential (ORP) of the polishing liquid is controlled so as to be in the range of 400 mV to 700 mV vs. Ag/AgCl.
Abstract translation: 一种制造半导体器件的方法，包括在绝缘膜上沉积包括Cu或Cu合金的互连材料，并用研磨液对CMP进行互连材料的研磨，其中研磨液的氧化还原电位（ORP）被控制 以相对于Ag / AgCl为400mV至700mV。
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公开(公告)号：US20070134899A1
公开(公告)日：2007-06-14
申请号：US11366511
申请日：2006-03-03
Applicant: Tsuyoshi Kanki , Nobuyuki Ohtsuka , Hisaya Sakai , Noriyoshi Shimizu
Inventor： Tsuyoshi Kanki , Nobuyuki Ohtsuka , Hisaya Sakai , Noriyoshi Shimizu
IPC: H01L21/44
CPC classification number: H01L21/3105 , H01L21/02063 , H01L21/76807 , H01L21/76814 , H01L21/76825 , H01L21/76828
Abstract: (a) A recess is formed through an insulating film formed over a semiconductor substrate. (b) After the recess is formed, a temperature of the substrate is raised to 300° C. or higher at a temperature rising rate of 10° C./s or slower and a first degassing process is executed. (c) After the first degassing process, a conductive film is deposited on the insulating film, the conductive film being embedded in the recess. (d) The deposited conductive film is polished until the insulating film is exposed. It is possible to suppress occurrence of defects during CMP to be performed after a conductive member is deposited on the surface of the insulating film having a recess formed therethrough.
Abstract translation: （a）通过在半导体衬底上形成的绝缘膜形成凹部。 （b）在形成凹部之后，以10℃/秒以下的升温速度将基板的温度升高至300℃以上，进行第一脱气处理。 （c）在第一脱气处理之后，在绝缘膜上沉积导电膜，导电膜嵌入凹部中。 （d）抛光沉积的导电膜直至暴露绝缘膜。 在导电构件沉积在具有通过其形成的凹部的绝缘膜的表面上之后，可以抑制在CMP期间发生的缺陷。
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公开(公告)号：US08691699B2
公开(公告)日：2014-04-08
申请号：US13427200
申请日：2012-03-22
Applicant: Tsuyoshi Kanki , Shoichi Suda , Shinya Sasaki
Inventor： Tsuyoshi Kanki , Shoichi Suda , Shinya Sasaki
IPC: H01L21/311
CPC classification number: H01L23/5389 , H01L21/4846 , H01L23/49822 , H01L24/19 , H01L24/20 , H01L24/96 , H01L2224/04105 , H01L2224/24137 , H01L2924/01029 , H01L2924/3511 , H01L2924/00
Abstract: A manufacturing method of a semiconductor device includes: forming an insulating layer above a substrate; forming a recessed section in the insulating layer; forming, on the insulating layer, a mask pattern having a first opening which exposes the recessed section, and a second opening which is arranged outside the first opening and does not expose the recessed section; forming a first conductive member and a second conductive member by respectively depositing a conductive material in the first opening and the second opening; and polishing and removing the first conductive member and the second conductive member on the upper side of the insulating layer so as to leave the first conductive member in the recessed section.
Abstract translation: 半导体器件的制造方法包括：在衬底上形成绝缘层; 在所述绝缘层中形成凹部; 在所述绝缘层上形成具有露出所述凹部的第一开口的掩模图案，以及布置在所述第一开口的外侧并且不露出所述凹部的第二开口; 通过在所述第一开口和所述第二开口中分别沉积导电材料来形成第一导电构件和第二导电构件; 并且在绝缘层的上侧抛光和去除第一导电构件和第二导电构件，以便将第一导电构件留在凹部中。
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公开(公告)号：US20120181070A1
公开(公告)日：2012-07-19
申请号：US13431127
申请日：2012-03-27
Applicant: Tsuyoshi Kanki , Yoshihiro Nakata , Yasushi Kobayashi
Inventor： Tsuyoshi Kanki , Yoshihiro Nakata , Yasushi Kobayashi
CPC classification number: H01L21/76877 , H01L21/02068 , H01L21/02071 , H01L21/02074 , H01L21/288 , H01L21/321 , H01L21/76834 , H01L21/76841 , H01L21/76852 , H01L21/76874 , H01L21/76883 , H01L21/76885 , H01L23/53238 , H01L2924/00 , H01L2924/0002 , H05K3/24
Abstract: After a copper interconnection is formed above a substrate, a surface of the copper interconnection is activated by performing acid cleaning. Thereafter, the substrate is immersed in a BTA (Benzo triazole) aqueous solution to form a protection film covering the surface of the copper interconnection. At this time, Cu—N—R bonds (R is an organic group) are formed in grain boundary portions in the surface of the copper interconnection. Thereafter, the protection film is removed by performing alkaline cleaning. The Cu—N—R bonds remain in the grain boundary portions in the surface of the copper interconnection even after the protection film is removed. Subsequently, the surface of the copper interconnection is subjected to an activation process, and a barrier layer is formed thereafter by electroless-plating the surface of the copper interconnection with NiP or CoWP.
Abstract translation: 在基板上形成铜互连之后，通过进行酸清洗来激活铜互连的表面。 此后，将基板浸入BTA（苯并三唑）水溶液中以形成覆盖铜互连表面的保护膜。 此时，在铜互连表面的晶界部分中形成Cu-N-R键（R为有机基团）。 此后，通过进行碱性清洗除去保护膜。 即使在保护膜被去除之后，Cu-N-R键也保留在铜互连表面的晶界部分中。 随后，对铜互连的表面进行激活处理，然后通过用NiP或CoWP对铜互连的表面进行无电镀来形成阻挡层。
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Patent Agency Ranking
6.发明申请METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND POLISHER USED IN THE METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权用于制造半导体器件的方法中使用的半导体器件和抛光剂的方法公开(公告)号：US20080166877A1
公开(公告)日：2008-07-10
申请号：US11968933
申请日：2008-01-03
Applicant: Tsuyoshi Kanki , Takahiro Kimura , Tetsuya Shirasu
Inventor： Tsuyoshi Kanki , Takahiro Kimura , Tetsuya Shirasu
CPC classification number: H01L21/76816 , H01L21/3212 , H01L21/7684 , H01L21/76873
Abstract: A method for manufacturing a semiconductor device, including depositing an interconnect material including Cu or Cu alloy over an insulating film, and polishing the interconnect material by CMP with a polishing liquid, wherein the oxidation-reduction potential (ORP) of the polishing liquid is controlled so as to be in the range of 400 mV to 700 mV vs. Ag/AgCl.
Abstract translation: 一种制造半导体器件的方法，包括在绝缘膜上沉积包括Cu或Cu合金的互连材料，并用研磨液对CMP进行互连材料的研磨，其中研磨液的氧化还原电位（ORP）被控制 以相对于Ag / AgCl为400mV至700mV。
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公开(公告)号：US20130093092A1
公开(公告)日：2013-04-18
申请号：US13613167
申请日：2012-09-13
Applicant: Tsuyoshi Kanki , Hideki Kitada
Inventor： Tsuyoshi Kanki , Hideki Kitada
IPC: H01L23/52 , H01L21/768
CPC classification number: H01L21/76883 , H01L21/7684 , H01L21/76849 , H01L21/7685 , H01L21/76877 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
Abstract: An electronic device includes: a first insulating film; an interconnection trench on a surface of the first insulating film; an interconnection pattern composed of Cu, the interconnection trench being filled with the interconnection pattern; a metal film on a surface of the interconnection pattern, the metal film having a higher elastic modulus than Cu; a second insulating film on the first insulating film; and a via plug composed of Cu and arranged in the second insulating film, the via plug being in contact with the metal film.
Abstract translation: 电子设备包括：第一绝缘膜; 在所述第一绝缘膜的表面上的互连沟槽; 由Cu构成的互连图案，互连沟槽填充有互连图案; 在互连图案的表面上的金属膜，所述金属膜具有比Cu更高的弹性模量; 第一绝缘膜上的第二绝缘膜; 以及由Cu构成并布置在第二绝缘膜中的通孔塞，所述通孔插塞与金属膜接触。
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8.发明申请公开(公告)号：US20130048358A1
公开(公告)日：2013-02-28
申请号：US13530815
申请日：2012-06-22
Applicant: Tsuyoshi KANKI , Shoichi Suda , Yoshihiro Nakata
Inventor： Tsuyoshi KANKI , Shoichi Suda , Yoshihiro Nakata
CPC classification number: H01L23/5389 , H01L23/49816 , H01L24/19 , H01L2224/12105 , H01L2924/01029 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T428/12993 , Y10T428/24355 , Y10T428/24463 , Y10T428/31515 , H01L2924/00
Abstract: A wiring structure includes: an insulating film formed over a substrate; a plurality of wirings formed on the insulating film; and an inducing layer, which is formed on the insulating film in a region between the plurality of wirings, a constituent atoms of the wirings are diffused in the inducing layer.
Abstract translation: 布线结构包括：形成在基板上的绝缘膜; 形成在所述绝缘膜上的多个布线; 以及在所述多个布线之间的区域中形成在所述绝缘膜上的感应层，所述布线的构成原子在所述诱导层中扩散。
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公开(公告)号：US20120273964A1
公开(公告)日：2012-11-01
申请号：US13427200
申请日：2012-03-22
Applicant: Tsuyoshi KANKI , Shoichi Suda , Shinya Sasaki
Inventor： Tsuyoshi KANKI , Shoichi Suda , Shinya Sasaki
IPC: H01L23/522 , H01L21/98 , H01L21/768
CPC classification number: H01L23/5389 , H01L21/4846 , H01L23/49822 , H01L24/19 , H01L24/20 , H01L24/96 , H01L2224/04105 , H01L2224/24137 , H01L2924/01029 , H01L2924/3511 , H01L2924/00
Abstract: A manufacturing method of a semiconductor device includes: forming an insulating layer above a substrate; forming a recessed section in the insulating layer; forming, on the insulating layer, a mask pattern having a first opening which exposes the recessed section, and a second opening which is arranged outside the first opening and does not expose the recessed section; forming a first conductive member and a second conductive member by respectively depositing a conductive material in the first opening and the second opening; and polishing and removing the first conductive member and the second conductive member on the upper side of the insulating layer so as to leave the first conductive member in the recessed section.
Abstract translation: 半导体器件的制造方法包括：在衬底上形成绝缘层; 在所述绝缘层中形成凹部; 在所述绝缘层上形成具有露出所述凹部的第一开口的掩模图案，以及布置在所述第一开口的外侧并且不露出所述凹部的第二开口; 通过在所述第一开口和所述第二开口中分别沉积导电材料来形成第一导电构件和第二导电构件; 并且在绝缘层的上侧抛光和去除第一导电构件和第二导电构件，以便将第一导电构件留在凹部中。
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公开(公告)号：US08101513B2
公开(公告)日：2012-01-24
申请号：US11366511
申请日：2006-03-03
Applicant: Tsuyoshi Kanki , Nobuyuki Ohtsuka , Hisaya Sakai , Noriyoshi Shimizu
Inventor： Tsuyoshi Kanki , Nobuyuki Ohtsuka , Hisaya Sakai , Noriyoshi Shimizu
IPC: H01L21/44
CPC classification number: H01L21/3105 , H01L21/02063 , H01L21/76807 , H01L21/76814 , H01L21/76825 , H01L21/76828
Abstract: (a) A recess is formed through an insulating film formed over a semiconductor substrate. (b) After the recess is formed, a temperature of the substrate is raised to 300° C. or higher at a temperature rising rate of 10° C./s or slower and a first degassing process is executed. (c) After the first degassing process, a conductive film is deposited on the insulating film, the conductive film being embedded in the recess. (d) The deposited conductive film is polished until the insulating film is exposed. It is possible to suppress occurrence of defects during CMP to be performed after a conductive member is deposited on the surface of the insulating film having a recess formed therethrough.
Abstract translation: （a）通过在半导体衬底上形成的绝缘膜形成凹部。 （b）在形成凹部之后，以10℃/秒以下的升温速度将基板的温度升高至300℃以上，进行第一脱气处理。 （c）在第一脱气处理之后，在绝缘膜上沉积导电膜，导电膜嵌入凹部中。 （d）抛光沉积的导电膜直至暴露绝缘膜。 在导电构件沉积在具有通过其形成的凹部的绝缘膜的表面上之后，可以抑制在CMP期间发生的缺陷。
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