摘要:
A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.
摘要:
A method of manufacturing a semiconductor device substrate includes the steps of: arranging on a base a temporary fixing member for temporarily fixing an electronic component; temporarily fixing the electronic component on the base by the temporary fixing member; forming a substrate body on the base and the electronic component; removing a portion of the base which portion corresponds to the electronic component, thereby exposing the temporary fixing member; and removing the temporary fixing member, thereby enabling the electronic component to make an external connection.
摘要:
A multi-layered circuit substrate for a semiconductor device comprises a multi-layered circuit substrate body having first and second surfaces and comprising a plurality of conductive pattern layers integrally laminated one on the other from the first surface to the second surface, so that a plurality of semiconductor device elements can be arranged on the first surface of the substrate body; and a plate member, a rigidity thereof being higher than that of the substrate body, attached to the second surface of the substrate body. A plurality of semiconductor elements can be mounted on the semiconductor element mounting surface defined on the first surface of the substrate body.
摘要:
An efficient substrate fabrication method is disclosed. A method of fabricating a substrate having a via terminal includes the steps of: forming a concave part on a front surface of a source substrate; forming a front surface side conductive part by filling the concave part with a conductor; forming the core substrate by back-grinding up to a position immediately before the front surface side conductive part is exposed such that a tip of the front surface side conductive part is covered with a portion of the core substrate; exposing the tip of the front surface side conductive part by forming a concave part in a rear surface of the core substrate; forming a rear surface side conductive part by filling the concave part with a conductor; and electrically and mechanically connecting the front surface side conductive part with the rear surface side conductive part.
摘要:
The invention is directed to a thin-film capacitor device that is adapted to be mounted on a printed wiring board together with an LSI device. After forming a plurality of grooves in a core substrate, a first conductive film is formed, and a first conductor is filled into each groove. After forming a metal film on the first conductive film, a dielectric film is generated by selective anodic oxidation of the metal film. A second conductive film is formed on the dielectric film, and an electrode connected to the second conductive film is formed. After removing the back surface of the core substrate until the grooves are exposed therein, an electrode for connection to the first conductor in each groove is formed. A capacitor is formed by the first conductive film and second conductive film sandwiching the dielectric film therebetween.
摘要:
A multilayer wiring substrate for providing a capacitor structure inside a multilayer wiring structure is disclosed. The multilayer wiring substrate includes a dielectric layer including a resin material mixed with an inorganic filler, wherein the inorganic filler is fabricated by mixing a paraelectric filler with an inorganic filler having a high dielectric constant.
摘要:
A wiring layer for serving as a first electrode layer of a capacitor portion patterned in a predetermined shape on an insulative base member is formed. A resin layer for serving as a dielectric layer of the capacitor portion is formed on a surface of the wiring layer using an electrophoretic process. Another wiring layer for serving as a second electrode layer of the capacitor portion patterned in a predetermined shape by patterning on the insulative base member inclusive of the resin layer is formed.
摘要:
A resin plate having wiring pattern recesses and via through holes is made. All of the surfaces of the resin plate including inner walls of the wiring pattern recesses and via through holes are coated with a metal film. An electro-plating is applied using the metal film as a power-supply layer to fill a plated metal into the wiring pattern recesses and via through holes. The metal film formed on the resin plate except for the inner walls of the wiring pattern recesses and via through holes is removed, so that wiring pattern and via are exposed on a surface the same as that of the resin plate.
摘要:
According to one embodiment, there is provided a semiconductor package manufacturing method utilizing a support body in which a first layer is stacked on a second layer, the method including: a first step of forming an opening in the first layer to expose the second layer therethrough; a second step of arranging a semiconductor chip on the second layer through the opening; a third step of forming a resin portion on the first layer to cover the semiconductor chip; and a fourth step of forming a wiring structure on the resin portion so as to be electrically connected to the semiconductor chip.
摘要:
A semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, wherein a topmost stacked structure of the multilayer interconnect structure includes a capacitor structure, the capacitor structure having a dielectric layer comprised of a mixed electrodeposited layer of high dielectric constant inorganic filler and insulating resin and including chip connection pads for directly connecting top electrodes and bottom electrodes with electrodes of the semiconductor chip, whereby greater freedom in design of interconnect patterns can be secured, the degree of proximity of the capacitor and semiconductor chip can be greatly improved, and the package can be made smaller and lighter in weight, a method of production of the same, and a semiconductor device using this semiconductor package.