公开(公告)号：US09064699B2

公开(公告)日：2015-06-23

申请号：US14258704

申请日：2014-04-22

Applicant: Wei-E Wang ,  Mark S. Rodder ,  Robert C. Bowen

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Robert C. Bowen

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/02488 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/66795

Abstract: Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods are provided. The methods may include forming an oxide layer on a substrate and forming a recess in the oxide layer and the substrate. The methods may further include forming an epitaxially grown semiconductor pattern in the recess that contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate.

Abstract translation: 提供了形成包括减少的位错缺陷的半导体图案的方法和使用这些方法形成的器件。 所述方法可以包括在衬底上形成氧化物层并在氧化物层和衬底中形成凹陷。 所述方法还可以包括在所述凹部中形成外延生长的半导体图案，所述外延生长的半导体图案在所述氧化物层和所述衬底之间的界面处接触所述衬底的侧壁，并且限定所述衬底的所述凹部中的空隙的上表面。

公开(公告)号：US07732102B2

公开(公告)日：2010-06-08

申请号：US11181169

申请日：2005-07-14

Applicant: Jonathan L. Cobb ,  Bernard J. Roman ,  Wei E. Wu

Inventor： Jonathan L. Cobb ,  Bernard J. Roman ,  Wei E. Wu

IPC: G03F1/00

CPC classification number: G03F1/34

Abstract: A photolithographic mask is adapted for use in imparting a pattern to a substrate. The pattern comprises a plurality of features. At least one of the plurality of features (201) is implemented in the mask as a phase shifting structure (205) with a unitary layer of opaque material (207) disposed thereon. The mask is utilized to impart the pattern to a layer over a semiconductor substrate.

Abstract translation: 光刻掩模适用于将图案赋予基板。 该图案包括多个特征。 多个特征（201）中的至少一个在掩模中实施为具有设置在其上的不透明材料（207）的整体层的相移结构（205）。 该掩模用于将图案赋予半导体衬底上的层。

公开(公告)号：US20080232346A1

公开(公告)日：2008-09-25

申请号：US12108268

申请日：2008-04-23

Applicant: Wei E ,  Rui XU

Inventor： Wei E ,  Rui XU

IPC: H04J3/06

CPC classification number: H04L41/5019 ,  H04L47/781 ,  H04L65/1069

Abstract: A method, a system and an apparatus for synchronizing the stream between the bearer control layer and bearer layer devices. Bearer layer device returns information corresponding to the stream synchronizing information distributed by the resource manager RM of the bearer control layer back to the resource manager RM (101, 102); when the resource manager RM determines that there is information needed to be synchronized included in the information returned by bearer layer device (103), it compares the information with the one held by itself (105), and performs synchronization to the information within the bearer layer devices that need to be synchronized according to the result of the comparison.

Abstract translation: 一种用于在承载控制层和承载层设备之间同步流的方法，系统和装置。 承载层设备将与承载控制层的资源管理器RM分配的流同步信息相对应的信息返回给资源管理器RM（101,102）; 当资源管理器RM确定需要被同步的信息包含在由承载层设备（103）返回的信息中时，它将该信息与其本身保持的信息进行比较（105），并且对承载层内的信息进行同步 需要根据比较结果进行同步的层设备。

公开(公告)号：US06902969B2

公开(公告)日：2005-06-07

申请号：US10632473

申请日：2003-07-31

Applicant: Olubunmi O. Adetutu ,  Hsing H. Tseng ,  Wei E. Wu

Inventor： Olubunmi O. Adetutu ,  Hsing H. Tseng ,  Wei E. Wu

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with a gate dielectric/etch stop layer stack. The N channel gate stack and the P channel gate stack are etched by a dry etch. Either the gate dielectric or etch stop can be in contact with the substrate. The etch stop layer prevents the dry etch of the first and second metal layers from etching through the gate dielectric and gouging the underlying substrate.

Abstract translation: 半导体器件具有包括第一金属类型的第一金属类型和第二金属类型的P沟道栅极堆叠以及包括与栅极电介质/蚀刻停止层堆叠直接接触的第二金属类型的N沟道栅极堆叠。 通过干蚀刻蚀刻N沟道栅极堆叠和P沟道栅极堆叠。 栅极电介质或蚀刻停止件可以与衬底接触。 蚀刻停止层防止第一和第二金属层的干蚀刻蚀刻通过栅极电介质并且刨削下面的衬底。

公开(公告)号：US09773906B2

公开(公告)日：2017-09-26

申请号：US15002078

申请日：2016-01-20

Applicant: Wei-E Wang ,  Mark S. Rodder ,  Ganesh Hedge ,  Christopher Bowen

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Ganesh Hedge ,  Christopher Bowen

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/764 ,  H01L21/02 ,  H01L21/308 ,  H01L29/04

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/3081 ,  H01L21/764 ,  H01L29/045 ,  H01L29/161

Abstract: Methods of forming a layer of silicon germanium include forming an epitaxial layer of Si1-xGex on a silicon substrate, wherein the epitaxial layer of Si1-xGex has a thickness that is less than a critical thickness, hc, at which threading dislocations form in Si1-xGex on silicon; etching the epitaxial layer of Si1-xGex to form Si1-xGex pillars that define a trench in the epitaxial layer of Si1-xGex, wherein the trench has a height and a width, wherein the trench has an aspect ratio of height to width of at least 1.5; and epitaxially growing a suspended layer of Si1-xGex from upper portions of the Si1-xGex pillars, wherein the suspended layer defines an air gap in the trench beneath the suspended layer of Si1-xGex.

公开(公告)号：US09218964B2

公开(公告)日：2015-12-22

申请号：US13198959

申请日：2011-08-05

Applicant: Gang Wang ,  Matty Caymax ,  Maarten Leys ,  Wei-e Wang ,  Niamh Waldron

Inventor： Gang Wang ,  Matty Caymax ,  Maarten Leys ,  Wei-e Wang ,  Niamh Waldron

IPC: H01L21/20 ,  H01L29/267 ,  H01L21/02

CPC classification number: H01L21/02538 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639

Abstract: Methods of manufacturing a III-V compound semiconductor material, and the semiconductor material thus manufactured, are disclosed. In one embodiment, the method comprises providing a substrate comprising a first semiconductor material having a {001} orientation and an insulating layer overlaying the first semiconductor material. The insulating layer comprises a recessed region exposing an exposed region of the first semiconductor material. The method further comprises forming a buffer layer overlaying the exposed region that comprises a group IV semiconductor material. The method further comprises thermally annealing the substrate and the buffer layer, thereby roughening the buffer layer to create a rounded, double-stepped surface having a step density and a step height. A product of the step density and the step height is greater than or equal to 0.05 on the surface. The method further comprises at least partially filling the recessed region with a III-V compound semiconductor material overlaying the surface.

Abstract translation: 公开了制造III-V族化合物半导体材料的方法以及如此制造的半导体材料。 在一个实施例中，该方法包括提供包括具有{001}取向的第一半导体材料和覆盖第一半导体材料的绝缘层的衬底。 绝缘层包括露出第一半导体材料的暴露区域的凹陷区域。 该方法还包括形成覆盖包括IV族半导体材料的暴露区域的缓冲层。 该方法还包括对衬底和缓冲层进行热退火，由此粗糙化缓冲层以产生具有阶梯密度和台阶高度的圆形的双阶梯形表面。 台阶密度和台阶高度的乘积在表面上大于或等于0.05。 该方法还包括用覆盖该表面的III-V族化合物半导体材料至少部分地填充该凹陷区域。

公开(公告)号：US20150093884A1

公开(公告)日：2015-04-02

申请号：US14258704

申请日：2014-04-22

Applicant: Wei-E Wang ,  Mark S. Rodder ,  Robert C. Bowen

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Robert C. Bowen

IPC: H01L21/02 ,  H01L21/762

CPC classification number: H01L21/02488 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/66795

Abstract: Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods are provided. The methods may include forming an oxide layer on a substrate and forming a recess in the oxide layer and the substrate. The methods may further include forming an epitaxially grown semiconductor pattern in the recess that contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate.

Abstract translation: 提供了形成包括减少的位错缺陷的半导体图案的方法和使用这些方法形成的器件。 所述方法可以包括在衬底上形成氧化物层并在氧化物层和衬底中形成凹陷。 所述方法还可以包括在所述凹部中形成外延生长的半导体图案，所述外延生长的半导体图案在所述氧化物层和所述衬底之间的界面处接触所述衬底的侧壁，并且限定所述衬底的所述凹部中的空隙的上表面。

公开(公告)号：US06232134B1

公开(公告)日：2001-05-15

申请号：US09490125

申请日：2000-01-24

Applicant: David Gerald Farber ,  Wei E. Wu ,  Phillip E. Crabtree

Inventor： David Gerald Farber ,  Wei E. Wu ,  Phillip E. Crabtree

IPC: H01L2100

CPC classification number: H01L22/20

Abstract: A method and apparatus for characterizing processing operations is presented. Following exposure of a wafer to plasma, the surface charge distribution pattern on the wafer is measured. The surface charge distribution pattern on the wafer is then compared with known surface charge distribution patterns to determine if the measured charge distribution pattern correlates to desirable patterns associated with successful performance of one or more processing steps. In some embodiments, the comparison of the measured charge distribution pattern can be used to detect specific problems in one or more processing steps such that corrective action can be taken in a timely manner. The comparison between the measured charge distribution pattern and known charge distribution patterns may be performed using image comparison or using quantitative comparisons based on charge levels measured within each pattern.

Abstract translation: 提出了一种用于表征处理操作的方法和装置。 在将晶片暴露于等离子体之后，测量晶片上的表面电荷分布图案。 然后将晶片上的表面电荷分布图案与已知的表面电荷分布图案进行比较，以确定测量的电荷分布模式是否与一个或多个处理步骤的成功执行相关联的期望模式相关。 在一些实施例中，所测量的电荷分布模式的比较可用于检测一个或多个处理步骤中的特定问题，从而能够及时地进行校正动作。 可以使用图像比较或使用基于每个图案中测量的电荷水平的定量比较来执行所测量的电荷分布图案与已知电荷分布图案之间的比较。

公开(公告)号：US5543362A

公开(公告)日：1996-08-06

申请号：US413037

申请日：1995-03-28

Applicant: Wei E. Wu

Inventor： Wei E. Wu

IPC: H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/823443 ,  H01L21/28052

Abstract: A process for fabricating refractory-metal silicide layers in a semiconductor device includes the formation of a composite gate electrode (54) and a buried contact structure (56). The composite gate electrode (54) includes a refractory-metal silicide layer (52) separated from a first polycrystalline silicon layer (38) by a diffusion barrier layer (46). The buried contact structure (56) includes a refractory-metal silicide layer (52) separated from a buried contact region (44) of a semiconductor substrate (30) by the diffusion barrier layer (46). The refractor-metal silicide layer (52) is formed by inverting a second polycrystalline silicon layer (48) to a refractory-metal silicide material while preventing the diffusion of refractory-metal atoms into underlying silicon regions.

Abstract translation: 在半导体器件中制造难熔金属硅化物层的工艺包括形成复合栅电极（54）和掩埋接触结构（56）。 复合栅电极（54）包括通过扩散阻挡层（46）从第一多晶硅层（38）分离的难熔金属硅化物层（52）。 掩埋接触结构（56）包括通过扩散阻挡层（46）与半导体衬底（30）的掩埋接触区域（44）分离的难熔金属硅化物层（52）。 折射金属硅化物层（52）通过将第二多晶硅层（48）倒置成难熔金属硅化物材料而形成，同时防止难熔金属原子扩散到下面的硅区域。

公开(公告)号：US09343303B2

公开(公告)日：2016-05-17

申请号：US14484511

申请日：2014-09-12

Applicant: Wei-E Wang ,  Mark Stephen Rodder

Inventor： Wei-E Wang ,  Mark Stephen Rodder

IPC: H01L21/3063 ,  H01L21/02 ,  H01L21/324 ,  H01L29/165 ,  H01L29/786

CPC classification number: H01L21/0262 ,  H01L21/02373 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02658 ,  H01L21/3063 ,  H01L21/324 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/786

Abstract: Methods of forming strain-relaxing semiconductor layers are provided in which a porous region is formed in a surface of a semiconductor substrate. A first semiconductor layer that is lattice-matched with the semiconductor substrate is formed on the porous region. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer being a strained layer as formed. The second semiconductor layer is then relaxed.

Abstract translation: 提供形成应变松弛半导体层的方法，其中在半导体衬底的表面中形成多孔区。 在多孔区域上形成与半导体衬底晶格匹配的第一半导体层。 第二半导体层形成在第一半导体层上，第二半导体层是形成的应变层。 然后放松第二半导体层。